Request Schematic review with ADA4939-1 and AD9258-125

Hello,

A few comments pertaining to the AD9258.

• Looking through schematic, I would suggest using the DCOA and DCOB signals since this is meant to be the latching signal for FPGA's input receiver.  One can connect this signal to one of the unused series resistors (used on data bit outputs) and route to FPGA with rest of data bits.
• With regard to decoupling capacitors for AVDD and DRVDD................I will assume that they exsit and are not shown in this section of schematic.
• The coupling caps at output of ADA4939-1  (C377-C380) can be reduced to 1 nF considering IF frequency is at 90 MHz.
• One could set  C392 and C409 to 1 nF such that one has a parallel 100nF//1nF combination that provides low common mode impedance (due to capacitor ESL) over wider frequency range.
• The CLK+/- differential input is biased internally at 0.9 V.   If the clock driver is DC coupled, make sure that the 0.9-1.4 V common-mode input range of the CLK+/- input is still met.

I will let one of my apps colleagues supporting ADC drivers comment on the ADA4939.