Connection to Xilinx KC705 from AD9625 Eva. Board

Dear Sir,

Our customer try to evaluate AD9625 Eva. Board (AD9625-2.0EBZ) using Xilinx KC705 by connecting FMC. However they can not establish the link of JESD204B by 4 lane. They use Xilinx JESD204B IP core. And they set up the registor of AD9625 to 4 lane ( 0x05E =0x04). Sampling rate is 1024Msps.

 

On the othere hand, the customer's board, which is used D9625, can establish the link to KC705 by 6 lane and 8 lane. But it also can not establish the link by 4.

 

Do you have any idea about the cause of this problem?

 

 

Best regards,

Akira 

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  • 0
    •  Analog Employees 
    on Aug 26, 2015 4:41 PM

    Hi Akira-

    For 4L configuration on AD9625, yes you will need to set register 0x05E = 0x04.  This will provide the data on the four lanes 0-3 by default.  Please confirm with your customer that the expectation of data within the KC705 is also on the 4 lower lanes of the 8L output SERDOUT[0-3].

    The sample rate of 1024MSPS is correct for the 4L configuration.  Please be sure that when the customer is validating this mode, that they invoke a reset of the device when changing from 8L to 4L.  This is needed whenever the sample rate is changed at the CLK input.

    Please also be sure that the IP is configured such that HD = 0 (High Density packing within the confines of JESD204B).  Also, the Frame Alignment Character Insertion is enabled by default.  If this is not expected in the FPGA receiver IP, it will cause issues.  This can be disabled in register 0x05F.

    Thanks,

    Ian Beavers

Reply
  • 0
    •  Analog Employees 
    on Aug 26, 2015 4:41 PM

    Hi Akira-

    For 4L configuration on AD9625, yes you will need to set register 0x05E = 0x04.  This will provide the data on the four lanes 0-3 by default.  Please confirm with your customer that the expectation of data within the KC705 is also on the 4 lower lanes of the 8L output SERDOUT[0-3].

    The sample rate of 1024MSPS is correct for the 4L configuration.  Please be sure that when the customer is validating this mode, that they invoke a reset of the device when changing from 8L to 4L.  This is needed whenever the sample rate is changed at the CLK input.

    Please also be sure that the IP is configured such that HD = 0 (High Density packing within the confines of JESD204B).  Also, the Frame Alignment Character Insertion is enabled by default.  If this is not expected in the FPGA receiver IP, it will cause issues.  This can be disabled in register 0x05F.

    Thanks,

    Ian Beavers

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