In the AD9649 data sheet, it mentions that a single-ended clock input can be used if the other input is bypassed to ground with a capacitor.
However, the data sheet only vaguely mentions what the tradeoffs / use cases for a single-ended clock would be: "In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 51). "
Is there any additional information about any more specific performance degradations in single ended configuration?
Thanks!
