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AD9649 single-ended clock

In the AD9649 data sheet, it mentions that a single-ended clock input can be used if the other input is bypassed to ground with a capacitor.

However, the data sheet only vaguely mentions what the tradeoffs / use cases for a single-ended clock would be: "In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 51). "

Is there any additional information about any more specific performance degradations in single ended configuration?

Thanks!

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  • Thanks for the comprehensive response, Doug. Definitely, these are all factors to consider when choosing to route single-ended vs differential.

    So based on your response, can I assume then that the comment on the data sheet was written primarily with board-level (routing) considerations in mind, rather than anything inherent to the ADC clock input buffer?

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  • Thanks for the comprehensive response, Doug. Definitely, these are all factors to consider when choosing to route single-ended vs differential.

    So based on your response, can I assume then that the comment on the data sheet was written primarily with board-level (routing) considerations in mind, rather than anything inherent to the ADC clock input buffer?

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