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AD9649 single-ended clock

In the AD9649 data sheet, it mentions that a single-ended clock input can be used if the other input is bypassed to ground with a capacitor.

However, the data sheet only vaguely mentions what the tradeoffs / use cases for a single-ended clock would be: "In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 51). "

Is there any additional information about any more specific performance degradations in single ended configuration?


  • Thanks for the comprehensive response, Doug. Definitely, these are all factors to consider when choosing to route single-ended vs differential.

    So based on your response, can I assume then that the comment on the data sheet was written primarily with board-level (routing) considerations in mind, rather than anything inherent to the ADC clock input buffer?

  • Yes, that's what I was asking - sorry if it was not clear initially.

    Thanks again for the help!

  • Hi Mr. Townley,

    Thank you for your interest in the AD9649.

    A single-ended clock will certainly work, but it has some disadvantages compared to a differential clock. Here is a quick, qualitative, non-comprehensive summary.

    Noise-Immunity: Additive noise will directly affect a single-ended clock, and thus negatively affect ADC performance. In contrast, additive noise will largely affect the common mode of a differential signal, i.e. both signals in a differential pair will be affected very similarly, but the difference between them will be largely unaffected. Because differential clock inputs largely react to the difference of the differential clock signals, and reject common-mode signals (Common Mode Rejection), a differential clock will be more noise immune.

    Slew Rate: Higher slew rate is beneficial for jitter considerations. Other things (drive strength, voltage swing, clock frequency) being equal, differential clocks will have a higher slew rate than single-ended clocks. This is because the single-ended clock is varying with respect to a non-varying quantity (often ground). Differential clocks vary in a complementary fashion (moving in opposite directions) with respect to each other, so their difference with respect to time (dv/dt) will be greater than the comparable single-ended case.

    EMI: Differential clocks will typically generate less EMI.

    Single-Ended clocks are simpler to route.

    The rationale is basically the same for differential clocks, and differential signaling in general.

    Depending on your system requirements, a single-ended clock may-or-may-not be adequate.

    Here are some additional related discussions:

    Frequently Asked Question | Analog Devices


    Frequently Asked Question | Analog Devices


    Clock Termination: Analog Dialogue: Analog Devices


    Thanks again for considering Analog Devices. I hope your project is a success.


  • Hi Mr. Townley,

    The comment in the datasheet alluding to the compromises with a single-ended clock are based on the inherent nature of single-ended clocks, which includes board considerations.

    I believe that the AD9649 clock input buffer works fine as a single-ended receiver, but single-ended by its very nature carries along with it some disadvantages that we have already discussed.

    Is this what you are asking?



  • You are very welcome.

    Your question was clear: I just wanted to double check.

    Thanks again!


  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin