Does ADI have document explain the relation between LO noise and these factors?
If I want to test output referred SNR (-153 dBc/√Hz) as datasheet setting (Test Conditions:−3 dBFS input, fRF = 2.5 MHz, f4LO = 10 MHz, 1 kHz offset). Does phase noise of 4LO affect test result? How clean LO should use?
3. Another question about AD9674 clock source. Do you have suggestion circuit (or IC ) that can suit for AD9674 sampling clock and CWD_LO requirement?
Does ADI have document explain the relation between LO noise and these factors?
If I want to test output referred SNR (-153 dBc/√Hz) as datasheet setting (Test Conditions:−3 dBFS input, fRF = 2.5 MHz, f4LO = 10 MHz, 1 kHz offset). Does phase noise of 4LO affect test result? How clean LO should use?
3. Another question about AD9674 clock source. Do you have suggestion circuit (or IC ) that can suit for AD9674 sampling clock and CWD_LO requirement?
