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CWD phase noise

Is there any 4LO phase noise requirement in Continuous Wave Doppler ultrasound of AD9278 ?

Thanks.

  • No there is no specific requirement for the 4LO phase noise related to the AD9278 itself, but CW Doppler system performance is affected by how clean the LO signal is. The analysis would be tricky though to quantify the impact and multiple design factors will affect it including correlation between Tx and LO signals and #ch for beam forming.

  • Thanks.

    1. Does ADI have document explain the relation between LO noise and these factors?
    2. If I want to test output referred SNR (-153 dBc/Hz) as datasheet setting (Test Conditions:−3 dBFS input, fRF = 2.5 MHz, f4LO = 10 MHz, 1 kHz offset). Does phase noise of 4LO affect test result?  How clean LO should use?

      3. Another question about AD9674 clock source. Do you have suggestion circuit (or IC ) that can suit for AD9674 sampling clock and CWD_LO requirement?

  • Unfortunately we don't have a document discussing LO noise impact on the CW Doppler system performance. However the rule of thumb is that the LO phase noise needs to be better than the target noise spec. For example when we measured our CW Doppler noise, we used a very clean LO clocking source, better than the 153 dBc/rt Hz that we measured.

    The LO multiplier factor will have an impact on how clean your LO source needs to be, for example to meet 153 dBc/rt Hz with a 16x MLO then the source needs to be better than 153-4 (multiplier factor) x3 (3dB per clock doubling)=141 dBc/rt Hz phase noise. If your source is 141 dBc/rt Hz then your system will be 3dB less than 153 dB/rt Hz since you have two sources of phase noise (LO & intern circuit) and the best you can get is 150 dB/rt Hz. To get the 153 then your LO needs to be even cleaner than 141, by another maybe 6 dB or so.

    If you use 4x LO then this puts more constraints on your LO source since you only relax the phase noise by 6 dB instead of 12 dB with 16x LO. For this example your LO source needs to be better than 153-2x3=147 dBc/rt Hz.

    For clocking solution, we suggest the AD951x family to drive the ADC clock, such as the AD9516. But I don't have a recommendation for the 4LO one and you may need to check on the clocking page of eZone.

    Thanks

    Ashraf

  • Thank you!

      This is great information for me to evaluate CWD function.