PN sequence in AD9246

hi, i have an AD9246 and i want to check the PN sequence of my device,

i enabled this config for my device with SPI, but i dont know how to check it?

and how can i measure the error? cross-talk of my board? and clock jitter

PLZ , help me


Best Regard

  • 0
    •  Analog Employees 
    on Oct 15, 2015 9:19 PM over 5 years ago


    The datasheet timing specs show set-up and hold times of the data relative to the rising edge of the DCO output signal that is used by the digital host to latch in the ADC data.  In the case of the 125 MSPS, the MIN specs are 2.6 and 3.7 nsec respectively although typical specs (i.e. 25 C , nominal supply, typical silicon device) provides more margin.   In other words,  data from the AD9246 is guaranteed to be stable (under all operating conditions) 2.6 nsec before DCO rising edge and remain stable for 3.7 nsec after rising edge.   Note, for the other speed grades.....this specification is further improved. is highly likely that this set-up and hold time exceeds what is required by the host device (FPGA).

    Use of PN sequence is one way of validating if you are capturing data correctly over a long period of time but is more complicated since one will need capture a long array of samples, find the seed, and time align captured data so it can be compared to original PN sequence to find "bit errors".   Perhaps an easier way to confirm data capture is to use the checker board pattern option where all bits transition on every clock cycle (but in checker board pattern).   Anyways, you should see a "checker board" pattern on your captured data output. 

    With regard to cross-talk..................I suspect you mean noise coupled into your ADC from other circuits on your PCB.  You can test by looking at the ADC's noise floor (without any input signal) and observe it shows any "spurious signals" or additive noise (beyond what you would expect from amplifiers, ext).

    With regard to jitter, you will need to use a high quality, low phase noise RF source that has been filtered (typically bandpass) along with a low phase noise clock source.  Set the input amplitude near the ADC's full-scale at the highest frequency that you intend on digitizing to observe any additive affects that may degrade the ADC beyond its own jitter contribution (0.1 psec rms).   How much additive close-in and wideband phase noise can be tolerated is application dependent.

    You can refer to this excellent white paper on selecting RF generators for testing ADC's.  

    Note, I think it is always good to confirm with an O'scope where one triggers off the DCO signal and then looks at all the data bits to see how they transition relative DCO.

  • Thanks dear

    I want to make a PN sequence and check with data come from ADC, How can i make it?

    I read some documents about making PN sequence but i confused

    i test my adc output without any input signal. the 4 lsb bits of adc is changing , i draw fft of the signals come from adc without any signals, the fft have peaks in Fadc/8,Fadc/4,.. and some other Frequency irrelevant to adc frequency how can i manage it?

    i use the setup time anf hold time in my Fpga but the output data capturef from FPGA dont seem changed from without consideration this timing constraint ?

    Thanx for your patient and time

    Best Regard

  • 0
    •  Analog Employees 
    on Oct 17, 2015 1:12 AM over 5 years ago


    I would suggest that you start debugging your digital interface with an easy digital data the checker board pattern that was suggested earlier.   Once you establish that you get the correct pattern captured by the FPGA, you can look at what occurs when you inject a signal.  Make sure that data format (i.e. 2's complement, or offset binary) matches FPGA. 

    You may want to consult one of your colleagues who may have some experience with ADC's also.