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AD9255 Production
The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance...
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AD9255 on Analog.com

AD9653 Recommended for New Designs
The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small...
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AD9255 PN9 and PN23 seed values



		

			

									
					    antgol
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 16, 2015 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi,
    
 
    I'm using AD9255 and try to validate digital interface with FPGA. So I'm checking different Output Test Modes. Positive and negative FS seems ok, alternating checkerboard seems ok, but PN sequences make me confused. PN9 is repeatable, is always the same after reset, but it is not as I expect. So I wonder about the seed value. In 9255 datasheet nothing is said about the seed, in AN877 Application Note the seed 0x092 is mentioned for all devices. But e.g. for AD9653 the seed value is all 1s. So what is correct for AD9255? And what 3 first numbers after reset should I get in 2-s complement mode (for seed 0x092 values should be x496, xFC9, xA99, correct?)? I wonder why AD does not make a simple counter as one of the test modes, it would be so much more convenient...
    
 

    
 
    Thank You
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 ad9653
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                                    
                 Standard High Speed A/D Converters
                
                                                    
                 ad9255
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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                on Oct 16, 2015 2:20 PM
            
            
					
        
	
        

		
		
        
					
        I made a simple vhdl to generate PN9 (in attachment), the sequence depends on the seed value and the bitwidth of the ADC.
        
 
        E.g. for 12-bit ADC and the seed 0x092 the first 3 outputs are:
        
 
        0x496, 0xFC9, 0xA99
        
 
        For 14-bit ADC and the seed 0x092 the first 3 outputs are:
        
 
        0x125B, 0x3C9A, 0x0C65
        
 
        For 14-bit ADC and the seed 0x1FF (all 1s) the first 3 outputs are:
        
 
        0x3FE0, 0x3DF1, 0x1CC8
        
 
        I'm still not sure about the seed value for AD9255
        
			
        

		
			
	      

		
				pn9.vhd.zip
			
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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							FormerMember
					
        
		
        
			
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									FormerMember
							        
			
			
			
      
            
						
                            
            
            				
            
                on Oct 16, 2015 7:46 PM
            
            
					
      
	
      

		
		
      
					
      Hello,
      
 
      I attached the Verilog code that describes the PN9 data path function used in the AD9255.  It appears that the seed is all 1's.  Hope this helps.
      
			
      

		
			
	      

		
				dpath_pn9.v.zip
			
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      


	

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                on Oct 17, 2015 11:00 AM
            
            
					
        
	
        

		
		
        
					
        PMH, thanks for your answer! Is this your code? It's seems a bit strange to me. The realization is not obvious, but the value of the shift register after each 14 shifts is the same as in my code: 1ef, 0e6, 04a etc. What I do not understand is why the output is formed directly from the current value of the shift register:
        
 
         assign out[15:0] = (mode) ? {xsreg[6:0], sreg[8:0]}: {xsreg[4:0], sreg[8:0], 2'b00};
        
 
        As far as I understand, each shift of the shift register produces 1 bit of the output (msb of shift reg), so after 14 shifts we have 14 output bits, while in a shift reg we have certain new 9 bits. So according to my simulation the first output should be 3FE0 (while current value of the shift reg is 1ef indeed).
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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