I have some questions about AD9650 for multi-chip sync.
What it means "A vaild SYNC causes the clock divider to reset to its initial state."?
How can reseting clock divider synchronize multiple ADCs?
This is from the Input Clock Divider section of the datasheet. The input clock divider is used when a system clock is provided to the AD9650 that is an integer multiple of the desired sample rate. The AD9650 input clock divider can divide by 2, 4, or 8 and therefore can accept a clock input that are multiples of 2, 4 or 8 times the desired sample rate. Because the divider is programmed through the SPI, it’s phase relationship is not deterministic and can vary for multiple devices on the same board and varies from startup to startup. To address this, a SYNC input is offered that allows for the resetting of the divider at a known instance. Applying a valid (and synchronized) SYNC signal to multiple AD9650’s would align the dividers in each and put them into a synchronized state.