I'm trying to get SerDes output from a set of AD9257's on a custom PCB.
1) No shorts on any pins
2) Correct SPI data and clock (running at ~1.5MHz)
3) Correct SPI register transmission settings things such as ADC digital reset and clock divider
4) Correct LVDS sample clock at 160MHz *(CLK_DIV = 4 for 40MS/s)
Upon board power up the ADCs do not yet have a correct clock, which here is coming from an AD9577 PLL. As such the DS indicates we need to issue an ADC Digital FSM reset to allow it to re-do its normal bias setup state machine. At the same time we set up other SPI registers with parameters such as test modes, duty cycle stabilization etc.
Now the problem is:
1) I currently cannot tell if the ADC SPI has actually changed the settings I want setting, and
2) DCO/FCO and all data lines seem to be held static at 0V (LVDS should have one high and one low right).
Now my current probe setup is 2 single-ended 1MOhm terminated probes. For the correct sample clock input the far end is already 100Ohm terminated. But for all FCO, DCO and data LVDS lines we are using the FPGA internal 100Ohm termination scheme.
Do I need to modify my measurement methodology to detect these LVDS signals, or is there an issue with the ADCs themselves. Any way to assess we are getting correct SPI modification of the internal registers, and any way to debug the outputs.