How to choose for read FIFO SPI interface for AD6641?

I'm trying to read FIFO SPI interface for AD6641 using AD6641-500EBZ Evaluation Board.  I'm clocking the part at 250MHz.  I followed the exact procedure from this post but it did not work.  After initiating the fill and reading the FIFO status register (0x10A), I get STATUS=0x04 (Over-range).  It doesn't matter when I read the status register, I always get Over-range.  I've never seen it empty or full.  How do I clear the FIFO status?  Do I need to write 0x00 to register 0x10A?

I'm trying to read FIFO SPI interface for AD6641 using AD6641-500EBZ Evaluation Board.  I'm clocking the part at 250MHz.  I followed the exact procedure from this post but it did not work.  After initiating the fill and reading the FIFO status register (0x10A), I get STATUS=0x04 (Over-range).  It doesn't matter when I read the status register, I always get Over-range.  I've never seen it empty or full.  How do I clear the FIFO status?  Do I need to write 0x00 to register 0x10A?

Hi, 

Resetting the FIFO should clear that register: 

write_reg(0x102, 0x04) // Fill Reset

Regards, 

David

I executed the example procedure exactly as written on this page except that I read_reg(0x10A) after each write.  As stated previously, the status always comes back 0x04 (Over-range) even immediately after write_reg(0x102, 0x04) // Fill Reset.  The only other thing that might be different about my code is that my write_reg() command contains a read_reg to verify the written value.  Do you expect this to cause problems?  Why else might the status always report over-range?  I'll try using a blindwrite command that doesn't verify the written value and see if that helps.

hello,

Did you find a solution to that problem?
I get the same error. My chip is always stuck on over-range in 0x10A.

The empty and the full are always inactive.

Thanks,

raphael

Hello Raphael,

I'm not 100% certain, but I think the solution was to do a hardware modification to the evaluation board.  I can see that I soldered wires on the board in the vicinity of the fill pins #49, #50.  I recall reading a post on this forum where someone said it's not good to leave those pins floating.  I think I pulled one high and the other low.  I hope this helps!

As long as I'm posting, I just want to share my opinion regarding the quality of design, implementation, and documentation for the AD6641 evaluation board and the chip in general.  The eval board schematic is poorly drawn, the layout is poorly executed, all aspects are poorly documented.  It looks like the work of an amateur or someone who has no pride in their work product.  The ADI SPI interface is a joke.  The datasheet has glaring errors in the SPI interface timing diagram (SCLK must idle high and serial data is clock-in on the first falling edge).  Despite this being a known datasheet error, it was not corrected when the datasheet was revised 3/2022.

Get it together ADI.   

Thanks for your answer. 
I think we found our issues.

The chip absolutely requires a dump reset (reg 0x102) to start correctly. The soft reset  (reg 0x00) is not enough.

(Also we had a problem with the chip driving the clock. Datasheet saying it is LDVS, but the chip really is LVPECL. It really seems that the overall quality of datasheets is getting very bad.)

raph