Post Go back to editing

How to choose for read FIFO SPI interface for AD6641?

1 How to choose for read FIFO SPI interface for AD6641? In which register of SPI and what values we need to write?

2 How to choose the SPORT interface? In which register of SPI and what values we need to write?

How to initialize a fill command through the SPI port without standby? In which register of SPI and what values we need to write?

4 How to use bits of the register 0x102?

Parents
  • Hi,

    Please ssee my answers in red below:

    1. On page 25 is not described in the operation Fill Reset and Dump Reset. What are bits 2 and 3 of the register 102?

    Bit 2 :This resets the state machines to await another FILL.  The FULL flag is reset

    and the  EMPTY flag is asserted

    Bit 3: This control resets pointer to original starting address for dump. 

    2.The controller performs a FIFO operation: I'm not sure what you are asking, does the procedure above not work for you?

    read_reg(0x10B)

    read_reg(0x10C) All the data array,

    write_reg(0x102, 0x00) // Clear the dump bit

    status = read_reg(0x10A) Read the status - Empty bit but no.

    Only if an additional 5 times to perform

    read_reg(0x10B)

    read_reg(0x10C) only then Empty bit there. Why?

    Run the following Filling only after Empty bit 1.

     

    Is it possible to reset the FIFO without additional operations read? Yes, you do not have to read back to reset the FIFO.

    3. The data sheet (FEATURES) indicated FIFO readback options SPORT at 62.5 MHz и SPI at 25 MHz. If AD6641 in a mode slave what can be maximal and minimal аrequency SP_SCLK and SCLK?  The SPORT and SPI are 2 different modes of reading back the data.  Through the SPI the max rate of transfer is 25MHz, I am not aware of a minimum requirement.  The SPORT can operate at 62.5MHz

    4. For what is used Vref?  This is a reference voltage for the ADC.  Most applications will use the internal reference, and this pin can float.


    Regards,

    David

Reply
  • Hi,

    Please ssee my answers in red below:

    1. On page 25 is not described in the operation Fill Reset and Dump Reset. What are bits 2 and 3 of the register 102?

    Bit 2 :This resets the state machines to await another FILL.  The FULL flag is reset

    and the  EMPTY flag is asserted

    Bit 3: This control resets pointer to original starting address for dump. 

    2.The controller performs a FIFO operation: I'm not sure what you are asking, does the procedure above not work for you?

    read_reg(0x10B)

    read_reg(0x10C) All the data array,

    write_reg(0x102, 0x00) // Clear the dump bit

    status = read_reg(0x10A) Read the status - Empty bit but no.

    Only if an additional 5 times to perform

    read_reg(0x10B)

    read_reg(0x10C) only then Empty bit there. Why?

    Run the following Filling only after Empty bit 1.

     

    Is it possible to reset the FIFO without additional operations read? Yes, you do not have to read back to reset the FIFO.

    3. The data sheet (FEATURES) indicated FIFO readback options SPORT at 62.5 MHz и SPI at 25 MHz. If AD6641 in a mode slave what can be maximal and minimal аrequency SP_SCLK and SCLK?  The SPORT and SPI are 2 different modes of reading back the data.  Through the SPI the max rate of transfer is 25MHz, I am not aware of a minimum requirement.  The SPORT can operate at 62.5MHz

    4. For what is used Vref?  This is a reference voltage for the ADC.  Most applications will use the internal reference, and this pin can float.


    Regards,

    David

Children
No Data