Post Go back to editing

How to choose for read FIFO SPI interface for AD6641?

1 How to choose for read FIFO SPI interface for AD6641? In which register of SPI and what values we need to write?

2 How to choose the SPORT interface? In which register of SPI and what values we need to write?

How to initialize a fill command through the SPI port without standby? In which register of SPI and what values we need to write?

4 How to use bits of the register 0x102?

Parents
  • Hi

    Thank you very much for your answer.

    1. On page 25 is not described in the operation Fill Reset and Dump Reset. What are bits 2 and 3 of the register 102?

    2.The controller performs a FIFO operation:

    read_reg(0x10B)

    read_reg(0x10C) All the data array,

    write_reg(0x102, 0x00) // Clear the dump bit

    status = read_reg(0x10A) Read the status - Empty bit but no.

    Only if an additional 5 times to perform

    read_reg(0x10B)

    read_reg(0x10C) only then Empty bit there. Why?

    Run the following Filling only after Empty bit 1.

    Is it possible to reset the FIFO without additional operations read?

    3. The data sheet (FEATURES) indicated FIFO readback options SPORT at 62.5 MHz и SPI at 25 MHz. If AD6641 in a mode slave what can be maximal and minimal аrequency SP_SCLK and SCLK?

    4. For what is used Vref?

    --
    Regards,
    СНК

Reply
  • Hi

    Thank you very much for your answer.

    1. On page 25 is not described in the operation Fill Reset and Dump Reset. What are bits 2 and 3 of the register 102?

    2.The controller performs a FIFO operation:

    read_reg(0x10B)

    read_reg(0x10C) All the data array,

    write_reg(0x102, 0x00) // Clear the dump bit

    status = read_reg(0x10A) Read the status - Empty bit but no.

    Only if an additional 5 times to perform

    read_reg(0x10B)

    read_reg(0x10C) only then Empty bit there. Why?

    Run the following Filling only after Empty bit 1.

    Is it possible to reset the FIFO without additional operations read?

    3. The data sheet (FEATURES) indicated FIFO readback options SPORT at 62.5 MHz и SPI at 25 MHz. If AD6641 in a mode slave what can be maximal and minimal аrequency SP_SCLK and SCLK?

    4. For what is used Vref?

    --
    Regards,
    СНК

Children
No Data