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How to choose for read FIFO SPI interface for AD6641?

1 How to choose for read FIFO SPI interface for AD6641? In which register of SPI and what values we need to write?

2 How to choose the SPORT interface? In which register of SPI and what values we need to write?

How to initialize a fill command through the SPI port without standby? In which register of SPI and what values we need to write?

4 How to use bits of the register 0x102?

  • Hi,

    Are you trying to use our evaluation kit  or design the part into  system?

    Regards,

    David

  • I try to use AD6641-500EBZ Evaluation Board without HSC-ADC-EVALCZ in the system.

    Regards,

    SNK

  • Hi,

    Here are some more specific answers:

    1 How to choose for read FIFO SPI interface for AD6641? In which register of SPI and what values we need to write?

    FIFO readback via SPI is always enabled with 0x107[1:0] = 0x00.

     

        write_reg(0x107, 0x00) // Set to SPI Readback

        write_reg(0x102, 0x04) // Fill Reset

        write_reg(0x102, 0x08) // Dump Reset

       

        n = int(floor(num_samples/64)) – 1

        write_reg(0x104, n) // Write the Number of samples.

        write_reg(0x102, 0x01) // Initiate FILL

     

        status = read_reg(0x10A)    // Read the status

     

        // Keep Reading the status until status[0] == 1 (full)

     

       write_reg(0x102 , 0x02) // Initiate dump

     

        int data_array[num_samples] // Initialize readback array

        for (int i=0 ; i < num_samples ; ++i) {

            low_byte = read_reg(0x10B)

            high_byte = read_reg(0x10C)

            data_array[i] = float(high_byte * 256 + low_byte)

        }

        write_reg(0x102, 0x00) // Clear the dump bit

    2 How to choose the SPORT interface? In which register of SPI and what values we need to write?  Set  address 0x107 [1:0] =10 for SPORT

      

     

    How to initialize a fill command through the SPI port without standby? In which register of SPI and what values we need to write?  To initiate a fill, set address 0x102[0] =1

     

     

    4 How to use bits of the register 0x102?     See above in (1).



    I would be interested to understand why you are not using the data capture card.  Was there a problem procuring this?


    Regards,

    David

  • Hi

    Thank you very much for your answer.

    Sorry for delay. My answer to your question

    I think, if in data sheet of the information are correct and full enough to build in system AD6641 simply.

      Harness the HSC-ADC-EVALCZ - expensive and not necessary.

    We are already working with the AD6641. We have following questions.

    1 What happens in the AD6641 when bits 2 and 3 entries in the register 102?

    2 Why for Empty signal should be after reading all the words from the FIFO to make 5 more 'empty' (code 0000) reads from the FIFO?

    3 If AD6641 in a mode slave what can be maximal and minimal SP_SCLK and  SCLK?

    4 What bit of the register can be controlled key CML (Figure 26 data sheet)?


    SNK

  • Hi,

    1 What happens in the AD6641 when bits 2 and 3 entries in the register 102?  These are the SPI controls that are equivelent to the ones described on page 25 for the external signals

    2 Why for Empty signal should be after reading all the words from the FIFO to make 5 more 'empty' (code 0000) reads from the FIFO?  I am not sure about this question, could you clarify?

    3 If AD6641 in a mode slave what can be maximal and minimal SP_SCLK and  SCLK?  The SP_SCLK is for the SPORT, not the SPI.  The max rate for the SPI interface is 40MHz, I do not think there is a minimum.

    4 What bit of the register can be controlled key CML (Figure 26 data sheet)?  We did not expect that there would be any dc coupled applications for this device, but it is possible to disable the dc bias of the Vin+/- by writing 0x04 to register address 0x2C. 


    Regards,

    David



  • Hi

    Thank you very much for your answer.

    1. On page 25 is not described in the operation Fill Reset and Dump Reset. What are bits 2 and 3 of the register 102?

    2.The controller performs a FIFO operation:

    read_reg(0x10B)

    read_reg(0x10C) All the data array,

    write_reg(0x102, 0x00) // Clear the dump bit

    status = read_reg(0x10A) Read the status - Empty bit but no.

    Only if an additional 5 times to perform

    read_reg(0x10B)

    read_reg(0x10C) only then Empty bit there. Why?

    Run the following Filling only after Empty bit 1.

    Is it possible to reset the FIFO without additional operations read?

    3. The data sheet (FEATURES) indicated FIFO readback options SPORT at 62.5 MHz и SPI at 25 MHz. If AD6641 in a mode slave what can be maximal and minimal аrequency SP_SCLK and SCLK?

    4. For what is used Vref?

    --
    Regards,
    СНК

  • Hi,

    Please ssee my answers in red below:

    1. On page 25 is not described in the operation Fill Reset and Dump Reset. What are bits 2 and 3 of the register 102?

    Bit 2 :This resets the state machines to await another FILL.  The FULL flag is reset

    and the  EMPTY flag is asserted

    Bit 3: This control resets pointer to original starting address for dump. 

    2.The controller performs a FIFO operation: I'm not sure what you are asking, does the procedure above not work for you?

    read_reg(0x10B)

    read_reg(0x10C) All the data array,

    write_reg(0x102, 0x00) // Clear the dump bit

    status = read_reg(0x10A) Read the status - Empty bit but no.

    Only if an additional 5 times to perform

    read_reg(0x10B)

    read_reg(0x10C) only then Empty bit there. Why?

    Run the following Filling only after Empty bit 1.

     

    Is it possible to reset the FIFO without additional operations read? Yes, you do not have to read back to reset the FIFO.

    3. The data sheet (FEATURES) indicated FIFO readback options SPORT at 62.5 MHz и SPI at 25 MHz. If AD6641 in a mode slave what can be maximal and minimal аrequency SP_SCLK and SCLK?  The SPORT and SPI are 2 different modes of reading back the data.  Through the SPI the max rate of transfer is 25MHz, I am not aware of a minimum requirement.  The SPORT can operate at 62.5MHz

    4. For what is used Vref?  This is a reference voltage for the ADC.  Most applications will use the internal reference, and this pin can float.


    Regards,

    David

  • I'm trying to read FIFO SPI interface for AD6641 using AD6641-500EBZ Evaluation Board.  I'm clocking the part at 250MHz.  I followed the exact procedure from this post but it did not work.  After initiating the fill and reading the FIFO status register (0x10A), I get STATUS=0x04 (Over-range).  It doesn't matter when I read the status register, I always get Over-range.  I've never seen it empty or full.  How do I clear the FIFO status?  Do I need to write 0x00 to register 0x10A?

  • Hi, 

    Resetting the FIFO should clear that register: 

    write_reg(0x102, 0x04) // Fill Reset

    Regards, 

    David

  • I executed the example procedure exactly as written on this page except that I read_reg(0x10A) after each write.  As stated previously, the status always comes back 0x04 (Over-range) even immediately after write_reg(0x102, 0x04) // Fill Reset.  The only other thing that might be different about my code is that my write_reg() command contains a read_reg to verify the written value.  Do you expect this to cause problems?  Why else might the status always report over-range?  I'll try using a blindwrite command that doesn't verify the written value and see if that helps.