AD9675 start code

I'd like to clarify how the AD9675 start code is overlaid onto the data stream; specifically:

  • Does the start code appear once per channel or once per lane?
  • If the latter, does it always appear on the lower channel (i.e., A on SERDOUT1, C on SERDOUT2, etc. assuming four-lane mode), upper channel, or either channel?

Thanks for your reply.

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    •  Analog Employees 
    on Feb 23, 2016 12:48 AM

    Hi Tony,

    There is latency between the TX_TRIG signal and the START_CODE as listed in Table 3 in the datasheet and in fact the output before START_CODE appears will be zeros. Figure 59 also shows the post ADC digital block will be idle (and output is zero) until the TX_TRIG pulse occurs. So you will not see the ADC output before the arrival of the global TX_TRIG pulse (or a soft TX_TRIG register write).

    The alignment of the channel data is guaranteed after the START_CODE if the global TX_TRIG pulse arrives to all chips at the same time. The order of the channel data per lane can be visualized using the attached spreadsheet for different operating conditions. You can enter the encode clock, decimation rate, #lanes, etc. and the spreadsheet will show the order of channel data per lane.

    I hope this is helpful and answer your questions.

    Regards

    Ashraf

    AD967x_SERDES_Output.xlsx
  • Hi, I have the AD9671's problem, when I set 0x188 to 0 ,the output is not zero , but when I set to 01 , the output is zero ,no matter how I config the register sequence of the AD9671 , I used software Tx_Trig , and ground the pin ,please help me ! this confused me for a lot time !

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