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AD9675 start code

I'd like to clarify how the AD9675 start code is overlaid onto the data stream; specifically:

  • Does the start code appear once per channel or once per lane?
  • If the latter, does it always appear on the lower channel (i.e., A on SERDOUT1, C on SERDOUT2, etc. assuming four-lane mode), upper channel, or either channel?

Thanks for your reply.

  • Hi Tony,

    Thank you for your interest in AD9675. The engineer who knows about this part is out-of-the-office today. I'm filling in and I'll pass along the information I've been able to gather.

    • The Start Code appears once per lane.
    • It appears before the first (or as you say, "upper") channel's data.

    In other words, for 4-lane mode:

    SERDOUT0: STARTCODE, CHA data , ChB data, ChA data, ChB data,….

    SERDOUT1: STARTCODE, CHC data , ChD data, ChC data, ChD data,….

    SERDOUT2: STARTCODE, CHE data , ChF data, ChE data, ChF data,….

    SERDOUT3: STARTCODE, CHG data , ChH data, ChG data, ChH data,….

    Thank you.


  • Hi Doug,

    Thanks for your reply. I'd like to verify one additional thing. Since the start code replaces a sample (data sheet Rev. A, p.31), I take it that the data before and after the start code looks like the following, thus retaining alignment of the channels within each lane. Is that correct?

    SERDOUT1: CHA data , ChB data, ChA data, STARTCODE, CHA data , ChB data,….

    SERDOUT2: CHC data , ChD data, ChC data, STARTCODE, CHC data , ChD data,….

    SERDOUT3: CHE data , ChF data, ChE data, STARTCODE, CHE data , ChF data,….

    SERDOUT4: CHG data , ChH data, ChG data, STARTCODE, CHG data , ChH data,….

    (The data sheet indexes SERDOUT from 1.)

  • Hi Tony,

    There is latency between the TX_TRIG signal and the START_CODE as listed in Table 3 in the datasheet and in fact the output before START_CODE appears will be zeros. Figure 59 also shows the post ADC digital block will be idle (and output is zero) until the TX_TRIG pulse occurs. So you will not see the ADC output before the arrival of the global TX_TRIG pulse (or a soft TX_TRIG register write).

    The alignment of the channel data is guaranteed after the START_CODE if the global TX_TRIG pulse arrives to all chips at the same time. The order of the channel data per lane can be visualized using the attached spreadsheet for different operating conditions. You can enter the encode clock, decimation rate, #lanes, etc. and the spreadsheet will show the order of channel data per lane.

    I hope this is helpful and answer your questions.



  • Hi, I have the AD9671's problem, when I set 0x188 to 0 ,the output is not zero , but when I set to 01 , the output is zero ,no matter how I config the register sequence of the AD9671 , I used software Tx_Trig , and ground the pin ,please help me ! this confused me for a lot time !