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AD9675 GPO polarity

When I write to the GPO register in the AD9675 (0x00E), I get the inverse of what I expect on the GPO pins (though I'm reading them indirectly through a connected FPGA). Each GPO has a 100 K pull-up attached to 1.8V. The register description in the data sheet (Rev A) says "Values placed on GPO0 to GPO3 pins"; but from what I see, setting any of these bits to 1 actually tells the corresponding open-drain driver to turn on, resulting in a logic zero. Is this actually the case?