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Troubleshooting AD9675 JESD204B link

The troubleshooting continues on our AD9675 design. We are unable to train/sync the JESD204B link. When we physically probe the SERDOUT± pins, we find they are static at 900 mV (common-mode voltage). We've checked that CLK± is running at 100 MHz and verified that PDWN and STBY are both low. We can read in and out of the SPI memory. One thing we've noticed is that SYNCINB± has a -300 mV differential (should be OK), but they are 1.0 V and 1.3 V (+/- respectively) thus not centered on the common-mode voltage of 0.9 V. Could this be an issue? And is there a troubleshooting checklist I can look at for this sort of problem?

  • The SYNCINB+- common mode range is limited to 0.9V to1.4V according to Table 2 in the datasheet. That could be the problem that the common mode is out of range and the part doe snot sense the assertion of the SYNCINB+-.

    The configuration seems to be correct for 100 MHz encode clock, one suggestion is to move the 0x142=0x01 to be after the 0x008=0x00 command since the 0x008 command will power up the JESD link coming out of the default power down mode. Also the SPI reset command will reset the 0x142 to default condition 0x00 anyway.

    There is no specific troubleshoot list but I am sure the general JESD troubleshooting material on Analog website could have useful information. I would say resolve the common mode issue first then observe the SERDOUT+- when the SYNCINB+- is asserted (active low), you should see  /K28.5/ characters.




  • Hi Ashraf,

    Thanks for your reply. One of our reps referred us to the JESD204B survival guide which includes troubleshooting suggestions starting on page 18. We eventually discovered that our SYNCINB± connections were reversed, and with the problem fixed our JESD link is now synchronizing.

    Thanks again,