Guys,
I have a customer evaluating AD9681. They would use EVAL-AD9681 which seems to connect with HSC-ADC-EVALDZ.
Can you give me the FPGA HDL code for this configuration?
Regards.
Matteo
Guys,
I have a customer evaluating AD9681. They would use EVAL-AD9681 which seems to connect with HSC-ADC-EVALDZ.
Can you give me the FPGA HDL code for this configuration?
Regards.
Matteo
Hi Teocrosio,
Sample FPGA capture code for the AD9681 is found here:
ftp://ftp.analog.com/pub/HSSP_SW/fpga/AD9681_Sample_FPGA_code.zip
This is written for Xilinx Virtex6.
This code is:
Thank you very much.
Doug
Hi Dougl,
How can I access the sample code?
Thanks
Hi akgulb,
Thanks for your interest in AD9681. I've requested that the sample code be emailed to you.
It is for the HSC-ADC-EVALEZ, which has replaced the .HSC-ADC-EVALDZ.
You should receive the code within a day or so.
Thanks,
Doug
Hi akgulb,
Thanks for your interest in AD9681. I've requested that the sample code be emailed to you.
It is for the HSC-ADC-EVALEZ, which has replaced the .HSC-ADC-EVALDZ.
You should receive the code within a day or so.
Thanks,
Doug