I have a customer evaluating AD9681. They would use EVAL-AD9681 which seems to connect with HSC-ADC-EVALDZ.
Can you give me the FPGA HDL code for this configuration?
Sample FPGA capture code for the AD9681 is found here:
This is written for Xilinx Virtex6.
This code is:
Thank you very much.
There is material available here: