I want to use the data clock output for FPGA at CMOS mode.I know the default mode is CMOS mode.
But,I find my DCOA and DCOB works at LVDS mode.
So how to deal with this problem?
AD9600
Production
The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS
ADC. It is designed to support communications applications
where low cost, small size, and versatility...
Datasheet
AD9600 on Analog.com
I want to use the data clock output for FPGA at CMOS mode.I know the default mode is CMOS mode.
But,I find my DCOA and DCOB works at LVDS mode.
So how to deal with this problem?
Hello,
The AD9600 should power-up in CMOS mode by default and would require a SPI write to bit 6 of Reg 0x14 to transform into LVDS. Are you stating that the AD9600 is powering up in LVDS mode? What is the voltage that you measure at data output pins since LVDS pins should be biased around 1.25 V?
Are you using the SPI port for programming? If so...........can you read back contents of Reg 0x14 to see if it indicates LVDS mode.?
Hello,
The AD9600 should power-up in CMOS mode by default and would require a SPI write to bit 6 of Reg 0x14 to transform into LVDS. Are you stating that the AD9600 is powering up in LVDS mode? What is the voltage that you measure at data output pins since LVDS pins should be biased around 1.25 V?
Are you using the SPI port for programming? If so...........can you read back contents of Reg 0x14 to see if it indicates LVDS mode.?