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Low Latency High-Speed ADC and DAC

Hi All,

One of my customer is looking for low latency high-speed ADC and DAC.

His application is to capture high frequency signal by high-speed ADC and the data is processed by FPGA and output control signal from the FPGA and is converted to high-speed DAC. This is a feedback control system for high frequency radar system testing.

Because of the feedback control system, the delay time from input of ADC to Analog output from high-speed DAC is very important.

His requirement is >=1GSPS, >=12bits, simple ADC and DAC function, no filtering and frequency converter are needed.

I picked up the following high-speed ADC and DAC for this application.

ADC

AD9234: 12 bit 1 GSPS, Delay min=55 clocks

AD9680: 14 bit 1.25 GSPS, Delay min=55 clocks

DAC

AD9789, 14 bit 2.4 GSPS, Delay min=7 clocks

AD9735/6, 12/14 bit 1.2 GSPS, Delay min=32 clocks

If you have any other recommendation for this application, please advise me.

Best Regards,

  Ricky

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  • Hi Ricky,

    I too am interested in a low latency high speed DAC for a fast feedback RF loop. No interpolation, no mixing, no FIFO, just balls to the wall speed. It's hard to find this for data rates greater than 750 MSPS.

    I'm also looking at the AD9736. Nice DAC, but how did you divine from the data sheet* that the minimum latency is 32 clock cycles?

    Best wishes,

    Tony

    *If someone from the DAC department of AD reads this please note that there's an error on Figure 77 ("Data Controllers", page 39) of the AD9736 datasheet. The clock coming into the top of the "CLK Control" block should be DACCLK, not DATACLK. Also in the formula below the diagram, the division ration is 2 to the power of CCD+4 (2^(...)) rather than 2 times CCD+4 (2(...)).

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  • Hi Ricky,

    I too am interested in a low latency high speed DAC for a fast feedback RF loop. No interpolation, no mixing, no FIFO, just balls to the wall speed. It's hard to find this for data rates greater than 750 MSPS.

    I'm also looking at the AD9736. Nice DAC, but how did you divine from the data sheet* that the minimum latency is 32 clock cycles?

    Best wishes,

    Tony

    *If someone from the DAC department of AD reads this please note that there's an error on Figure 77 ("Data Controllers", page 39) of the AD9736 datasheet. The clock coming into the top of the "CLK Control" block should be DACCLK, not DATACLK. Also in the formula below the diagram, the division ration is 2 to the power of CCD+4 (2^(...)) rather than 2 times CCD+4 (2(...)).

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