Post Go back to editing

AD9288 Digital Input Voltage Tolerance

Hello, I'm confused about the AD9288 datasheet specification for the voltage tolerance of the digital inputs.  Sheet 3 of the datasheet gives a minimum value for LOGIC-1 (2.0v).  However, the datasheet does not specify the maximum value for LOGIC-1.  Sheet 7 of the datasheet provides the absolute maximum specifications for the device (VDD + 0.5V). However, operating at the absolute maximum level is not recommended.

My plan is to tie VD and VDD of AD9288  to a 3.0V nominal supply.  However, the ENCA, ENCB inputs will be driven by a LVCMOS clock driver that is powered by 3.3v.  Therefore, the VOH of the clock driver will be 0.3v higher than VDD of the AD9288.  Is this a safe interfacing scheme?  If not what do you think about the following alternatives?

Alternative 1: Operate clock driver from a 3.0V power supply -- the same as AD9288 VDD supply.

Alternative 2: Operate clock driver at 3.3V    Operate AD9288 VDD = 3.3V      AD9288 VD = 3.0v

  • Hi gda,

    The AD9288 was released in early 1999 so the datasheet tends to reflect the documentation standards/practices that were common among semiconductor companies some 16+ years ago. Handily I was here at ADI back in 1999 so I think I can offer some "updated" insight into your inquiry...

    The AD9288 single-ended Encode input is specified for traditional TTL/CMOS compatibility. This means the Encode needs to fall between 0V and 0.8V to register as a logic "0", and between 2.0V and VD to register as a logic "1". The Analog VD, as well as the Digital VDD domains are specified for nominal operation at 3.0V but can safely operate between 2.7V to 3.6V.

    One thing to remember is that for our high speed ADC's the Encode is typically considered an "Analog" domain function since it basically controls the Analog front-end sampling switches and subsequent pipeline stages within the core of the ADC. The VDD is strictly used to bias the Digital Output Bit Drivers. Please refer to equivalent circuits Fig 23 and Fig 24 inserted below.

    As illustrated in Fig 23 the Encode input is diode clamped to both the VD and GND supply rails. The Digital Outputs are clamped in a similar manner to the VDD and GND supply rails. This is why the Abs Max Ratings for both the Encode as well as the other I/O pins are limited to -0.5V to Supply Rail +0.5V. Any termination levels exceeding 0.5V below GND, or 0.5V above the supply rail risks forward biasing these protection clamp diodes and potential electrical overstress.

    So keeping your CLK_Driver = VD = VDD = Receiver Logic I/O supplies the same will help mitigate potential issues related to inadvertently turning on the clamp diode structures. One downside to operating the Analog VD and Digital VDD from the exact same supply domain can be unintentional coupling of high current output switching noise back into the sensitive Analog Input where it can manifest itself as elevated noise/spurious. Diligent use of caps/chokes to isolate the VD and VDD connections from a common supply can prevent this issue.

    If separate supply domains are an option the best results may be achieved by running the CLK driver and ADC Core off 3.0V, and running the output driver VDD off a separate Digital 2.7V to 3.6V supply as dictated by the I/O signaling requirements of your receiver/buffer logic. Lower VDD will typically help reduce dynamic output switching noise. Remember to add some slew damping series resistors in the digital output lines as shown in the datasheet eval brd example to further suppress excessive switching noise.

    Please let me know if this addresses your questions.

    Best Regards,

    TonyM

  • TonyM,

    Thanks for your feedback.  You helped clear up the matter for me.

    The solution that I chose was to continue operating the ADC analog interface with 3.0v supply;

    and also operating the clock driver for the ENCA/B clock source at 3.3v supply.  However, a voltage

    divider was added at the between the clock driver output and the ADC ENCA/B input.  The voltage

    divider ensures that VOH should never exceed 3.0v at the ADC ENCA/B inputs.  I used a 50ohm series

    resistor, and a 500 ohm shunt resistor. This will create a 6mA current drain from the clock driver -- which

    is well within the capabilities of the clock driver.  I think that this will result in safe interfacing between

    the two devices.

    ... Thanks again for your help.

    gda