KCC's Quizzes AQQ305 about a mutual exponentiation equation
1. Quote of the month: "A train station is where a train stops. A bus station is where a bus stops. I have a work station on my desk, so..." - unknown
2. Quiz AQQ305 about finding a mutual exponential equation
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Quiz: How Well Do You Know Adaptive Power Switching?
Is your I/O module overheating? The AD74416H's Adaptive Power Switching (APS) can cut heat dissipation by up to 40% — but how well do you really understand how it works?
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AD9051
Production
The AD9051 is a complete 10-bit monolithic sampling analog-to-
digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed...
Datasheet
AD9051 on Analog.com
AD9631
Production
The AD9631/AD9632 are very high speed and wide bandwidth amplifiers. The AD9631 is unity gain stable. The AD9632 is stable at gains of 2 or greater. Using...
Datasheet
AD9631 on Analog.com
Hello ,
I use log detector (like AD8318) for pulse detection application. Applying detector output to ADC and which is sampled at 20MSPS and use this samples for further processing.
I use ADC part AD9051 in single ended ,DC coupled mode as shown below.
Problem here is output of AD9631 is inverted compared to Vin (with DC shift )and hence I need to use one more inverting amp to make ADC input compatible with Vin.
Please suggest simple solution for problem?
Thanks /
Shamanth
Hi Shamanth,
I discussed your inquiry with the AD9631 support team and the general consensus is that in order to maintain polarity unity with your system input you will either need to invert your signal with an additional unity gain amplifier stage before it goes into the AD9361, or digitally invert the output polarity post-conversion from the ADC within your receiver logic/FPGA.
Best Regards,
TonyM
Hi Shamanth,
I discussed your inquiry with the AD9631 support team and the general consensus is that in order to maintain polarity unity with your system input you will either need to invert your signal with an additional unity gain amplifier stage before it goes into the AD9361, or digitally invert the output polarity post-conversion from the ADC within your receiver logic/FPGA.
Best Regards,
TonyM