I have some questions with AD9625, We set the sample clock at 2.4GHz with AD9516 and ADCLK948, but the ad9625
cannot work correctly, the rx_sync and rx_tvalid go low always . we measure the swing of sample clock, it is 1100mv VPP at the source (ADCLK948), but it decline to 200mv VPP at the target (AD9625). we do not know why. is there some wrong with the termination? With this sample clock ,we use 200ohm pull down resistor at source (adclk948) ,0.1uf AC couple capacitor and 100ohm resistor placed betweeen P and N.at target(ad9625).
is there some wrong? Des AD9625 require 500mv or 250mv differential swing.sample clock? By the way, why AD9625 has 40Kohm input resistor?
Thanks very much !
Can anyone give me some advise?
Could you please share schematic to show how the AD9516, ADCLK948, and AD9625 are connected?
The recommended differential input clock voltage is between 500mV and1800mV. Please keep in mind that a lower clock swing would degrade SNR performance.
Thanks very much for you reply!
The clock tree is showing below:
The 100ohm termination resistor is placed close to AD9625. Is there something wrong? I measure the swing of CLKIN of ad9625 is just 200mv VPP and the sync and valid signal always go low. is it because low clock swing ?
Thanks very much!
The block diagram and the connections look good. Could you please share the clock path schematic? Are Vt and Vref connected together on the ADCLK948?
Could you please provide layout as well? How long is the trace between ADCLK948 and the AD9625?