ad9251

 I bough a HSC-ADC-EVALCZ capture  board  plus a AD9251 EVL. I wonder whether the start sampling signal is told to AD9251 through SPI? I need to output this signal through J5 and J7 simultaneously.

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    •  Analog Employees 
    on Aug 29, 2016 11:41 PM over 4 years ago

    Hi Yunqi,

    The AD9251 SPI is used to configure the ADC. When power and the clock are applied to the ADC, it is running continually. The AD9251 does not receive the start-sampling-signal by SPI.

    The FPGA receives the start-sampling-signal from your PC. I believe a new FPGA program would be needed to output the start-capture signal through J5 and J7.

    Unfortunately I do not know of an FPGA program that outputs the start-capture signal through J5 and J7. I'll check with the FPGA designer for suggestions. Please note that he is currently out-of-the-office so it will probably be about 1.5 weeks before I can get back to you.

    Thanks,

    Doug

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  • 0
    •  Analog Employees 
    on Aug 29, 2016 11:41 PM over 4 years ago

    Hi Yunqi,

    The AD9251 SPI is used to configure the ADC. When power and the clock are applied to the ADC, it is running continually. The AD9251 does not receive the start-sampling-signal by SPI.

    The FPGA receives the start-sampling-signal from your PC. I believe a new FPGA program would be needed to output the start-capture signal through J5 and J7.

    Unfortunately I do not know of an FPGA program that outputs the start-capture signal through J5 and J7. I'll check with the FPGA designer for suggestions. Please note that he is currently out-of-the-office so it will probably be about 1.5 weeks before I can get back to you.

    Thanks,

    Doug

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