Post Go back to editing

AD9864 Clock Synthetizer is not locking up to 18 MHz signal and also...

AD9864 Clock Synthetizer PLL is not locking up to 18 MHz that is supposed to after issuing the following SPI messages in the eval board using it's 26 MHZ clock reference and the exisiting varactor and loop filter:

0x3F 0x99  (RESET)

0x19 0x8C (Enable 4 wire SPI and config SSI Bus)

0x00 0x55 (Enable the LO and CLK Synthetizer modules)  [looks like CK = 1 for the clock to operate. correct?  I see the sine wave signal at 16.8MHz is the case with the scope on the output varactor.]

0x01 0x0C (Osc Bias = 0.65 mA, this creates the largest pk-pk sine wave in the varactor)

0x10 0x00 (Higher byte of CKR reference divider not used)

0x11 0x68 (Lower byte of CKR reference divider value of CKR = 104 to get 250 KHz phase detector sine wave from a 26 MHz external reference in the eval board)

0x12 0x00 (Higher byte of CKN VCO frequency divider not used)

0x13 0x48 (Higher byte of CKN VCO frequency divider value of CKR = 72 to get 250 KHz phase detector sine wave from a 18 MHz VCO in the PLL.

0x14 0x03 (Disable Fast Acquire, Positive VCO tunning, Charge Pump in normal operation.

What I am seeing is a 16.8 MHz sine signal at the VCO varactor that is not locked to 18 MHz that I would expect to settle within 0.01% of the final freq.  Why is this happening?

Please help.



  • Hi David,   

       I am moving the thread to the High speed ADC community. Someone here will be able to help you with your inquiry.



  • Hello,

    Referring to one of the example boot files ("16-bit IQ+AGC_FREF=26_CLK=18_LO SYN=107.5MHz_DEC=60.txt") that came with the AD9864 EVB software package, the following SPI commands were used to configure and boot the CLK SYN.  Note that Reg 0x00 is set to 0x45 (vs 0x55) so that both the CLK Oscillator and  SYN are enabled (i.e. set to "0").  Also, you will need also need to set Reg 0x3A to 0x08 if you want to readback SPI registers.


    3F 99

    3A 08

    19 87

    01 F8

    10 00

    11 68

    12 00

    13 48

    14 03

    00 45

  • Hello,

    I think I have the same problem. I wanted to set the Fclk to 14.4M, but no matter how I set the CKN, the FCLK is always 16.8M. (FREF = 19.2M, FLO = 71.1M, Decimation factor = 60)  

    Here is my register configuration.

    3F 99
    00 45
    01 0C
    03 80
    04 00
    05 00
    06 81
    07 00    (M=0 K=0)
    08 00
    09 C0  (LOR=192)
    0A E0 (LOA=7)
    0B 58 (LOB=88)
    0C 0B
    0D 00
    0E 0A
    10 00
    11 C0  (CKR=192)
    12 00
    13 90  (CKN=144)
    14 1F
    15 00
    16 0A
    18 40
    19 87
    1A 01
    3B 00
    1C 03
    00 44

    Please help.