AD9864 LC Tank Will Not Calibrate.

I am developing an application with the AD9864.  The majority of the example designs in the datasheet are exactly what I need (e.x. Fclk=18MHz,  +/-5Khz Decimation filter BW, 20Ksps, etc.), so I have followed the reference designs in the datasheet exactly.  All seems to be working more or less (the 18MHz VCO is fairly weak [~ 1Vpp, 1.6V DC offset] measured at pin 43 [LOP]), but I cannot not get the LC & RC Resonator Calibration to work.  I am following the script on page 46 of the datasheet exactly, however, when I send 0x03 to register 0x1C, most of the time it will lock up the SPI bus and force me to do a POR.  When it doesn't lock up the SPI, the value of 0x1C never clears.  The values of registers 0x1D, 0x1E remain 0x00.  Note that the values in the LC tank are exactly as recommended in the datasheet (50 Ohm, 2x 10uH, and 180pF).  Any help would be GREATLY appreciated.  We have been stuck on this issue for weeks now.  Note, R509 in the attached has been changed to 1.96K.

  • Hello,

    A few comments:

    1) Check if R505 is installed since a "floating" SYNCB that appears low would be issue (i.e. freezes internal clocks).

    2) A stable 18 MHz clock should appear at pin 19, CLKP.  Also, the IOUTC voltage should be close to mid-supply (i.e. not railed) thus suggesting CLK PLL is locked.  1 Vp.p.  is sufficient to trigger clock receiver and I assume that you modified CLKR setting since REFIN is 10 MHz vs datasheet example of 16.8 MHz.

    3) Can you confirm that you also write to 0x44 to Reg 0x1C   after you have written to 0x1C  (Step 14 and 15 in datasheet).

    4) Confirm that LC tanks are connected to device (i.e. cracked inductor, poor solder, ext).

    5) Send your SPI initialization to me for review.

    Regards.

  • Thanks for the quick response.

    1).  Verified.  R505 is installed.

    2).  Yes, 18MHz is present on CLKP.  I will verify the PLL control voltage on IOUTC.  Yes, CLKR divide ratio is set for 250KHz phase detector frequency (ie. divide ratio = 40, or 0x28).

    3) & 5).  The SPI Initialization Sequence is in the table below.

    4).  Confirmed a DC offset voltage is present on both side of the inductors.  I think they are good.  Problem has been duplicated on several Circuit Boards.

    Step

    Reg.

    Addr.

    Write

    Value

    Description

    1

    N/A

    N/A

    Verify that 10MHz is available to AD9864

    2

    0x3F

    0X99

    Command a SW reset to the AD9864 immediately after a POR by writing 0x99 to REG ADDR 0x3F (pg 19)

    3

    0x3A

    0x08

    Enable SPI Readback of AD9864 Registers

    4

    0x19

    0x8C

    Enable 4-wire SPI and config. SSI Bus:

    4_SPI (BIT7): Set to 1 to enable SPI reads with 4 wire interface.

    (BIT6:BIT4): Set to 0's – reserved

    DW (BIT3): Set to 1 for 24 bit I/Q data words, and set to 0 for 16 bit.

    DS (BIT2:BIT0): Set to 4 (100).  Increase if SSI interface is found to be unreliable.

    Config. 18MHz CLK Synth:

    5

    0x01

    0xF8

    CKOB (BIT3:BIT2): Set Osc. Bias to 0.35mA

    ADCB (BIT1:BIT0): Do not use.  Set to 00

    6

    0x10

    0x00

    CKR-MSB (BIT5:BIT0 of CKR MSB, but BIT13:BIT8 of 2 Byte CKR).

    7

    0x11

    0x28

    CKR-LSB (BIT7:BIT0 of CKR LSB, i.e. BIT7:BIT0 of 2 Byte CKR). Sets the 10MHz Ref. clock divider to 40, for  phase detector freq of 250KHz

    8

    0x12

    0x00

    CKN-MSB (BIT4:BIT0 of CKN MSB, but BIT12:BIT8 of 2 Byte CKN).

    9

    0x13

    0x48

    CKN-LSB (BIT7:BIT0 of CKN LSB, i.e. BIT7:BIT0 of 2 Byte CKN). Sets the 18MHz Fclock divider to 72, for  phase detector freq of 250KHz

    10

    0x14

    0x03

    CKF (BIT6): Set to 0 to disable Fast Acquire

    CKINV (BIT5): Set to 0 for positive VCO tuning input (i.e. increasing voltage increases frequency)

    CKI (BIT4:BIT2): Set to 0 for charge pump in normal operation: Ipump = (CKI+1)x0.625mA

    CKTM (BIT1:BIT0): Set to 11 (0x03) for normal control of CLK for charge pump.

    11

    0X00

    0X45

    Config STBY Register:

    REF (BIT7): Set to 0 to enable

    LO (BIT6): Set to 1 to keep disabled

    CKO (BIT5): Set to 0 to enable

    CK (BIT4): Set to 0 to enable

    GC (BIT3): Set to 0 to enable

    LNAMX (BIT2): Set to 1 to keep disabled

    Unused (BIT1): Set to 0

    ADC (BIT0): Set to 1 to keep disabled

    12

     

     

    Wait for CLK SYN 18MHz output to settle to within 0.01% of final freq.

    Begin LC & RC Resonator Calibration

    13

    0x3E

    0x47

    TEST (BIT7): Set to 0 (Factory test mode - Do not use)

    OVL (BIT6): Set to 1 (ADC Overload detector)

    TEST (BIT5:BIT3): Set to 000 (Factory test mode - Do not use)

    RC_Q (BIT2): Set to 1 (RC Q Enhancement)

    RC_BYP (BIT1): Set to 1 (Bypass RC Resonator)

    CS_BYP (BIT0): Set to 1 (Bypass SC resonators)

    14

    0x38

    0x01

    TEST (BIT7:BIT1): SET TO 0000000 (Factory test mode - Do not use)

    DACCR (BIT0): Set to 1  to enable Manual Feedback DAC Control

    15

    0x39

    0x0F

    DACDATA (BIT7:BIT0): Set to 00001111, set DAC to midscale.

    15.5

    0x00

    0x45

    Config STBY Register:

    REF (BIT7): Set to 0 to enable

    LO (BIT6): Set to 1 to keep disabled

    CKO (BIT5): Set to 0 to enable

    CK (BIT4): Set to 0 to enable

    GC (BIT3): Set to 0 to enable

    LNAMX (BIT2): Set to 1 to keep disabled

    Unused (BIT1): Set to 0

    ADC (BIT0): Set to 1 to keep disabled

    16

    0x1C

    0x03

    TUNE_LC (BIT1): Set LC tuning bit to 1

    TUNE_RC (BIT0): Set RC tuning bit to 1

     

    **SPI BUS FREQUENTLY LOCKS UP ON THIS COMMAND**

    17

    0X00

    0X44

    REF (BIT7): Set to 0 to enable

    LO (BIT6): Set to 1 to keep disabled

    CKO (BIT5): Set to 0 to enable

    CK (BIT4): Set to 0 to enable

    GC (BIT3): Set to 0 to enable

    LNAMX (BIT2): Set to 1 to keep disabled

    Unused (BIT1): Set to 0

    ADC (BIT0): Set to 0 to enabled

    18

    0x1C

    Read

    back value

    Wait 6 ms and read back Register 0x1C. If Register 0x1C clears, proceed to Step 18. If Register 0x1C does not clear, reset Register 0x1C and return to Step 15. Make five attempts before exiting loop.

     

    **IF SPI BUS DOES NOT LOCK UP, 0x1C READS 0x03**

    19

    0x38

    0x00

    TEST (BIT7:BIT1): SET TO 0000000 (Factory test mode - Do not use)

    DACCR (BIT0): Set to 0  to disable Manual Feedback DAC Control

    20

    0x3E

    0x00

    TEST (BIT7): Set to 0 (Factory test mode - Do not use)

    OVL (BIT6): Set to 0 (ADC Overload detector)

    TEST (BIT5:BIT3): Set to 000 (Factory test mode - Do not use)

    RC_Q (BIT2): Set to 0 (RC Q Enhancement)

    RC_BYP (BIT1): Set to 0 (Bypass RC Resonator)

    CS_BYP (BIT0): Set to 0 (Bypass SC resonators)

    21

    0x00

    0x00

    REF (BIT7): Set to 0 to enable

    LO (BIT6): Set to  0 to enable

    CKO (BIT5): Set to 0 to enable

    CK (BIT4): Set to 0 to enable

    GC (BIT3): Set to 0 to enable

    LNAMX (BIT2): Set to  0 to enable

    Unused (BIT1): Set to 0

    ADC (BIT0): Set to  0 to enable

  • By the way, what should I expect to see with an O-Scope on pin 5 IF2P?  Scenario:  172.25MHz, -40dBm single tone signal is present on the IF input. (IFIN, pin47, via P500 on schematic).  LO PLL is locked at 174.5MHz, so that IF is 174.5 - 172.25 = 2.25 MHz, or Fclk = 18MHz/8.  If the LC & RC calibrated successfully, shouldn't I see a 2.25MHz tone on pin 5, IF2P?

  • Hello,

    I attached an initialization script that works on my test set-up using the AD9864/74 EVB.  Note, the CLK/LO SYN was set for FREF of 10 MHz with Decimation Factor of 900 (IQ data at 20 KSPS with no embedded AGC).  Wait states have also been inserted per datasheet.  Let me know if this works.

    Regards.

  • Thanks for the new initialization script.  It will take a day or so for my SW engineer to implement the new init script.  I'll let you know in a day or so if it works.

    Thanks.