ADC9680CE04B evaluation Board Design Sources

Question

Hi, 
 We have downloaded the design sources of ADC9680CE04B from analog wiki.The download link is : https://wiki.analog.com/resources/eval/ad9680-1000ebz . 
 There are more mismatches between Schematic and BOM. 
 1.For example U402 in schematic it is indicated as ADM7160AUJZ-1.8 and in BOM it is ADP170AUJZ-1.25-R7. This is SPI power supply to AD9680. The output is always 1.25v beacuse of wrong part number. In AD9680 datasheet minimum Supply volatge to SPI is 1.8V. 
 2.In Schematic R416, R418, R420, R430 and R432 value is 66.5K but in BOM these are 56K. 
 We would like to know the design sources are latest or not. 
 Thanks & Regards 
 Rama Krishna

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UmeshJ · Answer

Hi, 
 (1) SPIVDD supports 1.25V also. So you can use either ADM7160 or ADP170. If you look at their schematics they both are pin compatible. 
 (2) The actual value is 56K. Follow the BOM. 
 The design files are the latest. 
 Thanks 
 Umesh

UmeshJ · Answer

Hello Rama Krishna, 
 SPIVDD supports 3.3V, so your proposal is ok. But SPIVDD can also be run at 1.25V if needed. We have characterized it to run at 1.25V. 
 I used 86.6k because the 1.25V domain had ferrite beads that had higher than normal DCR. So the only way to adjust for that was to bump up the voltage on the LDO. If you have a low enough DCR on your ferrite bead, then you can use the 84.5k. however, if the voltage drops too much, you will pay a penalty in AC performance (SNR/SFDR) or worse, the ADC might not even function. see Because Mr. Ohm Said So … | Analog Devices 
 C700 is actually a DNI as the BOM correctly says. It is only required if you are I/O limited on the FPGA and want to use a single ended REFCLK to the FPGA. 
 Thanks 
 Umesh

UmeshJ · Answer

Hi Rama Krishna, 
 If the chip is reading 0xFF then chances are, it is in some sort of POR. Have you measured the voltages at the pins (see Because Mr. Ohm Said So … | Analog Devices )? 
 It looks like you might be running SPI at 1.25V? is this correct? Not that this is an issue, but i think there seems to be some considerable noise on the SPIVDD. I would look at all the domains with a scope probe to make sure they are all "quiet". There is no way the chip can do such a thing to the CSB pin. 
 Are you seeing this on all the chips in your board? or only this specific one? 
 Thanks 
 Umesh

UmeshJ · Answer

Hi Rama Krishna, 
 If you are using the CE04B and SPI reads 0xFF when you try to read 0x003 (an odd numbered register) and 0x00 when you try to reach 0x004 (an even numbered register) it points to something wrong with the level translator buffer. That chip may either have blown, or not working. You have options here 
 1. Get the board replaced 
 2. Get the chip replaced (U601 = TXB0304) 
 3. Wire SPIVDD to 1.8V/2.5V to see if the buffer works now 
 Can you also check test point TP700 when the board is powered on? This is the VADJ and should read 1.8V when the board is powered on. 
 Thanks 
 Umesh

UmeshJ · Answer

Hi Rama Krishna, 
 Thank you for providing these graphs. I am not sure why the SPI lines are showing this weird behaviour. I am wondering if this could be due to the level shifter. One thing you can try to do is 
 - disconnect the SPIVDD by removing E409 
 - soldering a piece of wire between TP401 (AVDD_1P8) and E409 pin 2. 
 - you can also short the E409 pin 2 to AVDD2_TP (TP404) if you want 
 There is nothing inside the chip that should result in such behaviour in the SPI line. 
 Thanks, 
 Umesh

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ADC9680CE04B evaluation Board Design Sources