ADC9680CE04B evaluation Board Design Sources

Hi,

(1) SPIVDD supports 1.25V also. So you can use either ADM7160 or ADP170. If you look at their schematics they both are pin compatible. 

(2) The actual value is 56K. Follow the BOM.

The design files are the latest.

Thanks

Umesh

Hello Umesh,

@Thanks for the quick Response.

Due to logistic issues we made eval board from the sources given by ADI.

(1) SPIVDD supports 1.25V also. So you can use either ADM7160 or ADP170. If you look at their schematics they both are pin compatible. 

In the data sheet it is mentioned that it works from 1.7V to 3.3 Volts. So we are planning to remove the U402 and connect(short) pins1&5 so that we can use 3.3v as VDDSPI.

Please confirm it will work for 1.25v ? If it works then we will not go for reassembly.

In the schematic R417 mentioned as 100K and in the BOM it is 86.6K. If we are going for 86.6K then output volatge is

0.5*(1+(86.6K/56K))  = 1.273v .

Can we go for 84.5K(output voltage is 1.254v)instead of 86.6K? 

In the Schematic C700 capacitor for External refclk to FPGA not indiacted as DNI, but in BOM it is DNI.

please let me know whether we have to assemble C700 or not?

Thanks & Regards

Rama Krishna

Hello Rama Krishna,

SPIVDD supports 3.3V, so your proposal is ok. But SPIVDD can also be run at 1.25V if needed. We have characterized it to run at 1.25V.

I used 86.6k because the 1.25V domain had ferrite beads that had higher than normal DCR. So the only way to adjust for that was to bump up the voltage on the LDO. If you have a low enough DCR on your ferrite bead, then you can use the 84.5k. however, if the voltage drops too much, you will pay a penalty in AC performance (SNR/SFDR) or worse, the ADC might not even function. see  Because Mr. Ohm Said So … | Analog Devices 

C700 is actually a DNI as the BOM correctly says. It is only required if you are I/O limited on the FPGA and want to use a single ended REFCLK to the FPGA. 

Thanks

Umesh

Hello Umesh,

Thanks for the quick reply.

We will go with 86.6k resistor instead of 84.5k.

Regards

Rama Krishna

Hello Umesh,

I have done the job of reassembly ,Now all power supplies are good. But still SPI is giving 0xFF while reading register 0x0003(Chip type) ans 0x00 while reading 0x0004(CHIP_ID).

Is there any way to check AD9680 is out of POR?

Please see the Image above , which is Chip Select of AD9680, measured on Scope. I would like to know why such disturbance in the signal?

I have checked the voltage on SDIO and SCLK lines, which is 0 Volts.

Can u please give some suggestions for how to debug?

Thanks & Regards

Rama Krishna

Hi Rama Krishna,

If the chip is reading 0xFF then chances are, it is in some sort of POR. Have you measured the voltages at the pins (see Because Mr. Ohm Said So … | Analog Devices )? 

It looks like you might be running SPI at 1.25V? is this correct? Not that this is an issue, but i think there seems to be some considerable noise on the SPIVDD. I would look at all the domains with a scope probe to make sure they are all "quiet". There is no way the chip can do such a thing to the CSB pin.

Are you seeing this on all the chips in your board? or only this specific one?

Thanks

Umesh

Hi Umesh,

Thanks for the quick response.

Yes, We are using SPIVDD as 1.25v . I have check the voltage it is 1.25v & on scope there is no disturbances on the SPIVDD.

we are using eval board CE04B.

We have only one board. I have checked the voltages of all power rails  using multi metre. All power rails are in the range given in the data sheet. 

I will check all the power rails in Scope and will let you know.

SPI is giving 0xFF while reading register 0x0003(Chip type) ans 0x00 while reading 0x0004(CHIP_ID).

is it SPI block of ADC is not in acive state to respond?  

Thanks & regards

Rama Krishna

Hi Rama Krishna,

If you are using the CE04B and SPI reads 0xFF when you try to read 0x003 (an odd numbered register) and 0x00 when you try to reach 0x004 (an even numbered register) it points to something wrong with the level translator buffer. That chip may either have blown, or not working. You have options here 

1. Get the board replaced

2. Get the chip replaced (U601 = TXB0304)

3. Wire SPIVDD to 1.8V/2.5V to see if the buffer works now

Can you also check test point TP700 when the board is powered on? This is the VADJ and should read 1.8V when the board is powered on.

Thanks

Umesh

Hi umesh,

Thanks for the inputs.

I will get back to you after testing.

Thanks

Rama Krishna

Hi Umesh,

I have checked the voltage of VADJ at TP700, the value is 1.8v.

I have checked all voltage rails on scope. There are no distortions on the signal. Please look into the Images.

1. AVDD1

2. AVDD2

3.AVDD3

4.AVDD1_SYSREF

5. DVDD

6.DRVDD

7.SPIVDD

8.SCLK

9.SDIO

10.CSB

I have captured all the Images after giving power supply to the ADC Eval board. I am using ZC102 Zynq Eval Board as a master for SPI programming. I have configured FPGA in such  a way that it will drive logic 1 on CSB, SDIO and SCLK I/O's in idle state. But I have seen same behaviour as shown in above images. I have checked the CSB_FPGA_TO_DUT, It is giving 1.8v and in probe there are no distortions.

Regards

Rama Krishna