Could ADI please provide interface example/evaluation/test designs for AD9680 (AD9680-500EBZ) and Aria 10 SoC?
What design support/resources are available for Altera Aria SoC?
There exists no infrastructure for AD9680 on Altera platforms. All available HDL has been developed for ADS7-V2 which houses a Xilinx Virtex-7 FPGA.
I guess there is no chance that AD will release the HDL for the interface and JESD204B decoder to increase the speed of implementation on an Altera/Intel platform? If there was, that would be a very valuable help.