AD9648 goes in deadlock state at initialization

Hello,

 

In our current design, after multiple power ON/OFF, we face the issue that sometimes (~5%) we get the following situation:

 

  • AD9648 does not provide a valid output clock. (But input clock (based on DDS) is always OK)
  • AD9648 is no more resettable with digital reset.

 

In few words, AD9648 is in an undetermined state and can not recover.

 

This kind of problem were already reported here :

 

 

We modified our initialization sequence in several ways :

Trial 1 : Power up (All supplies start together) ->Clock input initialization (DDS based) -> ADC initialization (with digital reset)

Trial 2 : Power up (All supplies start together) ->ADC in full power-down mode -> Clock input initialization (DDS based) -> ADC initialization (with digital reset)

Trial 3 : Power up (All supplies start together) ->Clock input initialization (DDS based) -> No reset on ADC

 

No sequence improves our failure rate.

We are not able to prevent AD9648 to go in this undetermined state.

 

To better describe our hardware configuration : SYNC = PDWN = OEB = GND , VREF = VCM = GND, Clock input is differential

 

We need help or new ideas…

 

Thank you, Best regards,

Parents
  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:47 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
  • Hi

    may I know the solution to this problem? I am in the same trouble now.

    thanks

  • 0
    •  Analog Employees 
    on Aug 16, 2019 4:39 PM over 1 year ago in reply to wangdapeng

    Hi Wangdapeng,

    Here is some information on avoiding this situation.

    • Have your clock source up and stable when you power up AD9648
    • AD9648 has two power domains (AVDD, DRVDD). If your design allows for power supply sequencing, power up AVDD and bring the ADC sample clock to steady state before powering up DRVDD. In other words, bring up DRVDD last.
    • Reduce the size (capacitance) of the clock AC coupling capacitors by ≥10X. For example, if 0.1uF AC coupling clock capacitors are used, instead use 10nF. The smaller AC coupling capacitors decrease the time required for the clock to reach steady state at the ADC clock pins. Obviously, the AC coupling capacitors must be large enough to pass the clock signal.
    • If your system constraints do not allow adherence to these guidelines, is it possible to power-cycle DRVDD after your system is up and at steady-state? This accomplishes the same thing as bringing up DRVDD last.

    Please let me know if this solves your problem.

    Thanks,

    Doug

Reply
  • 0
    •  Analog Employees 
    on Aug 16, 2019 4:39 PM over 1 year ago in reply to wangdapeng

    Hi Wangdapeng,

    Here is some information on avoiding this situation.

    • Have your clock source up and stable when you power up AD9648
    • AD9648 has two power domains (AVDD, DRVDD). If your design allows for power supply sequencing, power up AVDD and bring the ADC sample clock to steady state before powering up DRVDD. In other words, bring up DRVDD last.
    • Reduce the size (capacitance) of the clock AC coupling capacitors by ≥10X. For example, if 0.1uF AC coupling clock capacitors are used, instead use 10nF. The smaller AC coupling capacitors decrease the time required for the clock to reach steady state at the ADC clock pins. Obviously, the AC coupling capacitors must be large enough to pass the clock signal.
    • If your system constraints do not allow adherence to these guidelines, is it possible to power-cycle DRVDD after your system is up and at steady-state? This accomplishes the same thing as bringing up DRVDD last.

    Please let me know if this solves your problem.

    Thanks,

    Doug

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