Hello,
In our current design, after multiple power ON/OFF, we face the issue that sometimes (~5%) we get the following situation:
In few words, AD9648 is in an undetermined state and can not recover.
This kind of problem were already reported here :
We modified our initialization sequence in several ways :
Trial 1 : Power up (All supplies start together) ->Clock input initialization (DDS based) -> ADC initialization (with digital reset)
Trial 2 : Power up (All supplies start together) ->ADC in full power-down mode -> Clock input initialization (DDS based) -> ADC initialization (with digital reset)
Trial 3 : Power up (All supplies start together) ->Clock input initialization (DDS based) -> No reset on ADC
No sequence improves our failure rate.
We are not able to prevent AD9648 to go in this undetermined state.
To better describe our hardware configuration : SYNC = PDWN = OEB = GND , VREF = VCM = GND, Clock input is differential
We need help or new ideas…
Thank you, Best regards,
Hi,
I can join some parts of the schematics.
Here is our AD9648 implementation :
Here is the DDS which drives ADC CLK inputs :
Thank you for your help,