AD9691 Sample Synchronization

We are interested in AD9691 multichip synchronization, with different decimation rates being used in different channels, either within the same chip or between chips. The JESD204B link guarantees deterministic latency across the link, but does not consider latency in the adc front end core.

It is understood that the JESD Link, input clock dividers and downconverter NCOs can be synchronized. However, does the chip provide deterministic latency from sample capture time to the time a sample is input into the JESD204B link? Is this true for the scenario described (channels across multiple chips running at different decimation rates)?

The datasheet does not seem to address the timing of the ADC front end core. Figure 4 shows an example timing sequence for one particular set of options (L=8,M=2,F=1) but with no text description and no description of timing for other options.

Thanks,
Scott

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  • 0
    •  Analog Employees 
    on May 23, 2017 2:29 PM

    Hi Scott,

    The deterministic latency as defined in the JESD204B specification does take into account the core's latency as well. If you provide a edge synchronous clock and SYSREF signal to the ADC, the control bits are inserted into the bit stream pertaining to the sample that corresponded to the rising edge of the clock that coincided with the SYSREF pulse. So, when the receive logic gets the SYSREF signal decoded, you are getting the entire latency of the pipe, digital block as well as the JESD204B interface. 

    In your scenario, the multichip synchronization should work the same way as if there were no decimation. the only thing the decimation adds is some extra latency owing to the processing of the bits as they pass through the various filters. You can also use different decimation rates in the various filters and still attain subclass 1 operation. 

    Thanks

    Umesh

Reply
  • 0
    •  Analog Employees 
    on May 23, 2017 2:29 PM

    Hi Scott,

    The deterministic latency as defined in the JESD204B specification does take into account the core's latency as well. If you provide a edge synchronous clock and SYSREF signal to the ADC, the control bits are inserted into the bit stream pertaining to the sample that corresponded to the rising edge of the clock that coincided with the SYSREF pulse. So, when the receive logic gets the SYSREF signal decoded, you are getting the entire latency of the pipe, digital block as well as the JESD204B interface. 

    In your scenario, the multichip synchronization should work the same way as if there were no decimation. the only thing the decimation adds is some extra latency owing to the processing of the bits as they pass through the various filters. You can also use different decimation rates in the various filters and still attain subclass 1 operation. 

    Thanks

    Umesh

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