My design is four AD9625 chips working at 2.4GHz sampling frequency, the clock is provided by a HMC7044 chip. After sampling the data sent to the FPGA, AD9625 TX JESD204B protocol configuration for the 8 LANES, F = 1, K = 32, Scrambling. The FPGA receiving section of the JESD204B IP uses the same configurations.
However, the situation I encountered was that the SYNC signal at the FPGA receiver was always logic 0. We can receive K characters from the physical layer of GTH.
Then, I measured the AD9625's supply pin voltage (4 AD9625 parallel power supply, current is not restricted) and found that when the AD9625 in RESET mode, the pin voltage is normal, when the AD9625 work, the pin's supply voltage drops 0.12V (FROM 1.26 DOWNTO 1.14).
Now, I think the above speculation is not correct, but I could not find other reasons. Can you give me some help to solve this problem? Thank you!!!
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