Products Mentioned

AD9680 Recommended for New Designs
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold...
Datasheet
AD9680 on Analog.com

Associated Drivers

AD9860 Not Recommended for New Designs
The AD9860 / AD9862 are versatile integrated mixed signal front ends that are optimized for broadband wireless applications. The AD9860 / AD9862 are cost...
Datasheet
AD9860 on Analog.com

HMC7044 Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
Datasheet
HMC7044 on Analog.com

Associated Drivers

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Length Matching requirement for JESD204B

		            
		

			

									
					    vish1ram
					
							


			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jun 23, 2017 
				
			
			
		
    
		
     
				
		
    
		    		    
		    
		    	
			
    Hi All,
    
 
    I am working on AD9680 ADC, which is using JESD204B subclass 1 for data transfer. We made custom board which has AD9860 ADC and HMC7044 for clocking. In our setup receiver is Xilinx FPGA Board(zynq ultrascale+). 
    
 
    I have few queries  for length matching requirements of ADCLK and SYSREF of devices.
    
 
    1. is ADCCLK and SYSREF from HMC7044 to ADC9680 should be length matched?
    
 
    2.is FPGA CORECLK and  SYSREF from HMC7044 Should be length matched?
    
 
    3. is All the clocks (ADCCLK, ADC-SYSREF, FPGA CORECLK and FPGA-SYSREF) from HMC7044 should be length matched?
    
 
    We have 4 ADC (AD9680) chips on our board. Is it required for length matching of all Clocks and SYSREF for synchronization?
    
 
    Thanks & Regards
    
 
    Rama Krishna
    
									
			        
		
    

				
						
        

    
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                 ad9680
                
                                                    
                 Clock Generation Devices
                
                                                    
                 ad9860
                
                                                    
                 Clock Generation and Distribution
                
                                                    
                 hmc7044
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jun 23, 2017 1:52 PM
            
                                    
					
      
	
      

		
		
      
					
      Since the HMC7044 has the ability to adjust the phase of both SYSREF and device clock, the trace length matching requirements are very relaxed.  There are 17 steps of 25ps analog phase adjust. (The analog phase delay adds some phase noise which is not a problem for lower frequency SYSREF).  So, all SYSREF’s can be adjusted to arrive within 25ps of each other using the analog phase delay.  You can’t totally disregard trace length matching.  17x25ps = 475ps of adjustment, so, trace length should match to within 2.5 inches (if using FR4 material)  for most accurate sysref placement.  I have attached the slides from a webinar that covered this topic.  They were made before we had the HMC7044 but the concept is the same. 
      
			
      

		
			
	      

		
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                on Jun 27, 2017 6:34 AM
            
                                    
					
        
	
        

		
		
        
					
        Hi Jones,
        
 
        I have a query regarding the delay adjustment in HMC7044. There is a digital delay setting in HMC7044 by which we can adjust the delay by half clock cycles of fvco. I am using internal vco of HMC7044. My internal vco is tuned to 3.2GHz and I am using a divider to get an output of 320MHz clock which I am feeding to my ADCs. My queries are as below.
        
 
        1. Here fvco is the output of the internal vco (3.2GHz) or the clock output (320MHz)?
        
 
        2. Can we use this delay also for doing the phase adjustment of clocks to different devices?
        
 
        Thanks and Regards,
        
 
        Kiran
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Jun 29, 2017 11:19 AM
            
                                    
					
        
	
        

		
		
        
					
        Kiran,
        
 
        fvco represents the output of internal VCO - or indeed the frequency of VCO. Yes, digital delay does not cause any noise degradation so it can be used both on ADC clocks and on SYSREF signal for phase adjustments.
        
 
        Regards,
        
 
        Kazim
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
				
						
						
				
				
		
		
        
			
		
        
	
        

        

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