We are currently trying to configure and debug AD9684 in byte mode. For now we are using 2 DDC (DDC0 and DDC1) which are configured as follows:
Register address data
x311 x00 (I and Q inputs from CH A)
x331 x05 (I and Q inputs from CH B)
We are using LVDS byte mode with two converters (reg x568 x15).
But when we apply RF power to CH A input we are seeing zeros (x0000) in I0 and I1 positions (according to Figure 9 of datasheet) and identical sine pattern both in Q0 and Q1.
When we apply RF power to CH B input we are still seeing zeros in I0 and I1 and some noise floor both in Q0 and Q1.
We've managed not to see zeros in I0 and I1 only when changed mixer from real to complex for both DDC0 and DDC1, but still it will only react on power on CH A input, but not on CH B input. And all four I0, Q0, I1 and Q1 looks the same, none of them are quadrature to other.
Also we used user patterns to try to understand what's happening and when we wrote x05 in register x327 (both I and Q test outputs of DDC0 are enabled) we saw our test patterns in all four I0, Q0, I1 and Q1 positions in output frame. When using DD1 test outputs there is nothing on the output.
When cofiguring input from CH B for DD0 and input from CH A for DDC1 we are seeing the same picture but now for CH B and CH A (or DDC1) is ignored.
I'm including file with register map we are currently using. Could you please look into it and explain us what we have to do to see converted data from bath CH A and CH B inputs simultaneously.
Last question: could it be a typo in register address of last register in Table 29 of datasheet (output parallel driver adjust 2)? Could it be not x05B, but x56B? And if yes, could the fact we are now writing x00 in wrong register x05B cause troubles?
I am glad to hear you were able to get things moving and apologize for the delay in the original response. You are correct that the AD6679 and AD9680 are similar parts. The AD6679 would be closer to the AD9684 but is not the same part as it is intended for different markets and applications. The output LVDS modes however would be pretty much the same between the AD9684 and AD6679.
As for the DDC soft reset it is shown in the register map that 0 = normal operation and 1 = reset. The SPI Soft reset in register 0x00 is indicated as self-clearing and the intention is that if the register is not noted as self-clearing then the register needs to be written back to normal operation after a reset.
The AD9684 does allow for operating 2 DDCs in complex mode (4 virtual converters) with decimate by 16 but a timing diagram is not shown for that particular mode. The timing would be similar to Figure 10 in the AD9684 data sheet. The output line rate would be 250 Mbps (8 x fout where fout = (sample rate)/(decimation ratio)) and you'd have I0 (Even), I0(Odd), I1(Even), I1(Odd), Q0(Even), Q0(Odd), Q1(Even), and Q1(Odd) bits per frame. The DCO would be running at 125 MHz and the frame clock would be running at 31.25 MHz. You can refer to Table 35 of the AD6679 for the LVDS output configurations. The dotted lines on the clock are to differentiate between the + and - of the differential clock.
Your comments on the data sheet are noted and appreciated. A data sheet revision is in order indeed, but unfortunately I do not have a timeline on that completion date that I could provide at this time.
I would also encourage you to take a look at two of my Analog Dialogue articles to better understand the DDC operation. You can find them here: http://www.analog.com/en/analog-dialogue/articles/whats-up-with-digital-downconverters-part-1.html and here: http://www.analog.com/en/analog-dialogue/articles/whats-up-with-digital-downconverters-part-2.html. I also have several blogs related to DDCs on the Planet Analog site.