I have a question regarding the HSC-ADC-EVALEZ and AD9656.
Currently I can use Visual Analog to capture RF signal center frequency @~ 64Mhz with AD9656, through HSC-ADC-EVALEZ. However, with Visual Analog, I can only use the mouser to click start acquisition button( which should be implemented via SPI ).
I would like to capture a RF frequency sweep signal( RF duration~ 1ms, frequency span~=800Khz, center frequency=64Mhz). And I would like a gated signal to trigger the acquisition window. With gated signal, I can align the TX frequency sweep signal exactly with my acquisition window.
I am thinking if ADI already offered some demo code of the HSC-ADC-EVALEZ. If so it must be easier for me to customize( maybe I can connect one of SMA connector to a gated TTL signal) while I do not need to program the Virtex-6 from the beginning.
Thank you for using the AD9656.
Please review this post ( https://ez.analog.com/thread/50358 ) and see if this gives any information that is relevant to your application.
Thanks for the reply. That paper is very helpful and I can use the external trigger now.
Futhremore, that paper does not talk about the clock syncronization issue. From my understanding, that 80Mhz cystal@ AD9656 EVAL board(the board that I have installed a 80Mhz crystal,instead of 125Mhz) offered the original internal clock, which is dissipated to the FPGA board. Is that correct?
Now I am using ROHDE SCHWARZ SMBV100A as the RF signal source( to generate that RF sweep signal). That souce has a 10Mhz reference clock IN and OUT.
I woud like the TX system(Here the SMBV RF source) can share the same clock with the aquisition system(here the AD9656). Currently I would still like the ADC sampling frequecy as 80Mhz. Hence I have two questions:
1. Does HSC-ADC-EVALEZ offer a port to receive an external 10Mhz clock? or it can offer a 10Mhz ref clock to drive the SMBV100A signal source?
2. Do you have any paper talking about the clock syncronization chain regarding AD9656 EVAL and HSC-ADC-EVALEZ? I would like to make sure my understandings correct.
The 80MHz crystal oscillator provides the sample clock to the AD9656. There is some additional hardware on the AD9656 evaluation board that uses the ADC sample clock to generate a reference clock for the FPGA. The frequency of this reference clock for the FPGA depends on the JESD204B configuration being used.
I'm sorry but I'm not understanding your questions.
Please let me clarify:
In order to align the TX and RX system, (here the TX is RF signal generator and RX is ADC), I need to align two things, the gated signal and the clock. The gated signal controls when to start and end( normally on the scale of several mili seconds). And the clock signal controls the delta phase of the TX and RX. If signal generator shares the same clock with ADC, then relative phase difference between signal generator and ADC output will be fixed, whenever I start the test, the phase is fixed.
If the TX and RX have their individual clock, the phase of ADC out relative to the TX will dither every time.
1. That 80Mhz crystal on the AD9656 EVAL board is the source for HSC-ADC-EVALEZ. Hence I can consider that 80Mhz crystal as the clock for ADC, the RX system. In order to align the TX system clock with that 80Mhz crystal, I can do two things:
a. connect that 80Mhz crystal output to my signal generator
b. configure an external clock to FPGA board and makes the FPGA board to offer a clock to ADC board( the opposite way as now in AD9656).
method A does not need extra configuration for AD9656 and HSC-ADC-EVALEZ but it is harder to implement on signal generator and other equipment. Most signal generators ask for 10Mhz instead of 80Mhz.
Method B is the way that I want. It is easier to play on equipment but harder to configure the ADC and FPGA board. But I am not sure if that is feasible.
2. I would like to use a 10Mhz clock to syncronize the below things:
a. signal generator( to generator that RF sweep signal)
b. the ADC aquisition system
c. the gate signal generator.
Thanks for your explanation. I'm sorry, but I'm still not clear on several aspects.
You state that "That 80Mhz crystal on the AD9656 EVAL board is the source for HSC-ADC-EVALEZ." The FPGA board has its own clock sources. You are correct that the 80MHz clock from the crystal oscillator is the sampling clock for the ADC.
Are you trying to synchronize the sampling clock to your signal generator? If so, a 10MHz clock from the FPGA board will not be aligned with any particular sampling instant. The sampling instant is determined by the 80MHz clock to the ADC and not by any clocks going to or from the FPGA. FPGA related clocks will be more relevant to capturing digital output data from the ADC, and not related to the ADC sampling the analog signal.
The ADC sampling clock and FPGA related clocks affect two different parts of the signal chain.
Perhaps a block diagram of your intended system would help.
Again, I apologize for my not understanding this.