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AD9218 Production
The AD9218 is a dual 10-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits. The product is low cost, low power, and...
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AD9218 on Analog.com

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AD9218 Power Supplies



		

			

									
					    JPSmith
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Sep 15, 2017 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi,
    
 
    I'm wondering about the timing requirements regarding the analog and digital supplies for the AD9218.
    
 
    Can these supplies be initialized at different times? Must one come before the other if so?
    
 
    Are there any effects of supplying two different voltages?
    I'm planning on supplying the analog side, Vd, with +3V and the digital side, Vdd, with +3.3V. The +3.3V will come up a few ms after the +3V. Is this acceptable?
    
 
    Thanks
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 ad9218
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                                    
                 Standard High Speed A/D Converters
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Sep 27, 2017 6:07 PM
            
            
					
      
	
      

		
		
      
					
      Hi Jim,
      
 
      The outputs should only enter Hi-Z mode when the power-downs are asserted.  At startup, the first five samples are random.  The internal latches and flops are not reset to a known state so the part will flush the datapath as the initial valid samples propogate through the pipeline.
      
 
      Best Regards,
      
 
      TonyM
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Sep 27, 2017 6:07 PM
            
            
					
      
	
      

		
		
      
					
      Hi Jim,
      
 
      The outputs should only enter Hi-Z mode when the power-downs are asserted.  At startup, the first five samples are random.  The internal latches and flops are not reset to a known state so the part will flush the datapath as the initial valid samples propogate through the pipeline.
      
 
      Best Regards,
      
 
      TonyM
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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