I didn't succeed to capture AD9208 data using the attached test setup and the following test conditions: Fclock = 2625MHz, FPGA global clock = 328.125MHz, Full BW mode, L=8, M=1, F=1, N'=16 (as recommended in the wiki page). The clock signals have generated with an AD9530 PLL evaluation board. I have used this ACE installer version : http://swdownloads.analog.com/ACE/ACEInstall_1.7.2585.1050.exe
I have the same issue with an AD6688 eval board. When I click on run once button the SW didn't stop without displaying any error message. Please advice asap as my project is blocked due to this issue ...
My mistake, I have confused the J3 connector on ADS7 with the J3 connector of the eval board !
AD6688 board works fine. However, I have a PLL lock issue with AD9208.
I am glad you were able to get the evaluation board for AD6688 to work by changing it to J3 of the FPGA board. J3 of the evaluation board is used for other purposes.
When you say you have a PLL lock issue with AD9208, are you saying that the AD9208 cannot detect a PLL lock? meaning 0x056F reads 0x00? Can you please read back 0x056E and let me know what it reads?
Thank you for your feedback.
Both PLL lock detect on ACE GUI and register read indicate that AD9208 PLL
does not lock.
As AD6688 works fine with the same setup, it means that there is an issue
with AD9208 eval board.
I will return the eval board to distributor for replacement.
with Kind Regards
Ok. Can you try another register read on the AD9208? The clock detect register 0x011B?
I will do ...