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AD9467 rms noise

Dear ,  I would like to explain the problem about the noise obtained from the AD9467 evaluation board:

I am using FMC AD9467 250MSPS ADC for sampling 200KHz signal as input with the ZC706 zynq FPGA. The ADC is being operated at 250MSPS sampling rate and I capture million samples correctly. I am using the AIN inverted input with the ADL 5562 amplifier (configured for obtaining a gain value 1) for the AD9467 ADC input.The problem comes from the noise because I obtain 10 ADU rms noise when no signal is connected to the input (50ohm). It is a very high noise.

Could this noise come from the ADC clock? A sine signal 240Mhz obtained from a signal generator was used for connecting  to the CLK input ADC board.Have you got any comments or suggestion to do? Should I use the ad9517 to clock the ad9467 on the AD9467-FMC-250EBZ board?

Thanks in advance 

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  • I used the ADL5562 option, using the configuration of figure 36 as I have attached in the circuit2 file. For doing this test, I connected AMPOUT+, AMPOUT- to AIN+,AIN-. I alsoremoved R119 and R120 in order to isolate the AIN input stage to the ADC. (see UG-200.pdf). Using this configuration, I obtained 9.66ADU with the interposer and the ZC706.

    Other test: I also removed any intput to the ADC and 4.5 ADU rms noise was obtained. So I concluded that 9.66-4.5ADU is the noise induced from the ADL5562

    Thanks

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  • I used the ADL5562 option, using the configuration of figure 36 as I have attached in the circuit2 file. For doing this test, I connected AMPOUT+, AMPOUT- to AIN+,AIN-. I alsoremoved R119 and R120 in order to isolate the AIN input stage to the ADC. (see UG-200.pdf). Using this configuration, I obtained 9.66ADU with the interposer and the ZC706.

    Other test: I also removed any intput to the ADC and 4.5 ADU rms noise was obtained. So I concluded that 9.66-4.5ADU is the noise induced from the ADL5562

    Thanks

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