Currently I try to connect the AD9694-500EBZ to the ZCU102 Zync Ultrascale evaluation kit. On the FPGA reference design page I see some user guides for different FMC-boards that provide a good starting point but unfortunately the AD9694-500EBZ board is missing. On the github page it seems there is some recent development taking place for these two boards. For example with a downloaded design from github I was able to (easily) build a project with the AD9680 ADC for the ZCU102 board. Another approach is to use the reference design for the AD9694 but that is not targeted the ZCU102 board. My question is:
What is, according to you, a good starting point to get the AD9694 working with the ZCU102 board?
- "Wait" for the github development?
- Start "hacking" in the different ref designs to reuse the JESD204 interface, ADC spi interface, FPGA transceivers and Linux tools?
We just added support for the AD9694 to reference HDL and driver projects last week. Currently the HDL support resides in a special branch called dev_ad9694. See GitHub - analogdevicesinc/hdl at dev_ad9694
The only carrier support at the moment is the ZC706. We'll probably not add official support for other carriers at this point in time. But you should be able to add support for the ZCU102 yourself using maybe the other ZCU102 based designs. Also see Porting ADI's HDL reference designs [Analog Devices Wiki] for some ideas how to port a design from one carrier to another.
The main difference will be how the different pins are connected. SPI and other control pins as well as the high-speed transceiver lanes. Otherwise from a HDL point of view things should be pretty much the same. JESD204 specifies the rules how the data is encoded so the decoding is the same for the AD9680 and the AD9694. On the dev_ad9694 branch we introduced a generic core called axi_adc_jesd204 that can handle all ADI JESD204 converters. You only have to specify the number of lanes, converters, etc. that you are using.
One of the things that will probably will be different is the clocking. You need to provide a sample point to the converter and a reference clock to the FPGA. While the AD9694-EBZ board has a clock input for the FPGA reference clock it is not powered up in the default configuration and needs a re-work. So it might be easier to directly connect the clock to the FPGA. The ZCU102 has a differential MGT_CLK input that can be used for this.
Another thing that will be different is the software. The AD9694 has register map that is different from the AD9680 and requires a different initialization sequence.
The AD9694 has an internal divider on its clock input, which can either be set to 1, 2, 4 or 8. The external clock must run at X times the desired sample rate (where X is the setting of the divider). The default divider configuration is 2, so if your desired sample rate is 500 MSPS the correct rate for the external is 1GHz.
Which configuration you want to use for the clock divider depends on your requirements and the quality of the external clock. Bypassing the clock divider and using a lower reference clock can result in lower power consumption in your clock generator. Using the built-in clock divider on the other hand can improve the quality of the clock signal.
The reference clock for the high-speed transceiver depends on the JESD204 lane rate and should be either lane_rate/40 or lane_rate/20 in subclass 0 operation or lane_rate/40 in subclass 1 operation. A higher reference clock rate can improve the performance of the high-speed transceiver (less bit errors), but typically performance is good enough even with lane_rate/40. If you want deterministic latency you need to provide the reference clock at lane_rate/40 or a dedicated device clock. This is necessary to guarantee a deterministic phase for the clock that clocks the JESD204 receiver logic in the FPGA.
The lane rate depends on the number of lanes, the number of converters, the octets per sample and the sample rate of the converter. The relationship here is to multiply number of converter, octets per sample and sample rate, than divide by number of lanes and multiply the whole thing by 10. So in case of 2 lanes, 2 converters and 2 octets per frame and sample rate of 500 MSPS that is ((2 * 2 * 500 MSPS) / 2) * 10 = 10 Gbps. So lane_rate/20 is 500 MHz and lane_rate/40 is 250 MHz.
The SYSREF signal is only required in subclass 1 operation when deterministic latency is required. For now I'd recommend to setup your system in subclass 0 and ignore the SYSREF signal (tie it to 0 in the FPGA reference design). In general the SYSREF should be a down divided version of the so called local-multi-frame-clock (LMFC). Typically sample rate divided by a power of 2 larger than 128 works fine.
The JESD204 receiver (or transmitter) chain in the FPGA consists of multiple components. The axi_jesd204_rx is the link component and the axi_adc_jesd204 is the transport layer component. For more see JESD204 Interface Framework - FPGA HDL support [Analog Devices Wiki].
Sorry, ZC702 support was a mistake on my side, only the Arria 10 SoC board from Intel is supported at the moment by the AD9694 design. But only the design itself is Intel FPGA specific, all the AD9694 specific components used in the reference design are also available for Xilinx based platforms.
Thanks for the tips regarding the clocking! After I've modified the system_constr.xdc to match the (FMC connector of the) AD9694-500EBZ I think I can build a project and hopefully see some activity in the transceiver.
A bit more about the clocking:
- So, for the AD9694 sample clock I'll use an external clock source @1GHz, correct?
- for the transceiver the MGT ref clk from the ZCU102 brd. @500MHz, correct?
- What to do with the rx_sysref clock? What is the frequency coming out the AD9523 on FMCDAQ2/3 board? Any idea on which clock I should use?
- What is the difference between the axi_adc_jesd204 that you propose and the https://github.com/analogdevicesinc/hdl/tree/dev_ad9694/library/jesd204? They are both supported in software?
- Above you've mentioned the support for the ZC706 carrier, I cannot find that on branch dev_ad9694. Is it on git?
Thanks again for your help,