• State Verified Answer
  • Replies 1 reply
  • Subscribers 43 subscribers
  • Views 531 views
  • Users 0 members are here
Options
Related 

        

            Post
             Go back to editing
        

    

    


    

    









		











	
	
			
	
			
		
	
	
		

		
Clock interface of AD9635



		

			

									
						BCAO
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Jan 22, 2018 
				
			
			
		


				
		

		    		    
		    
		    	
			
The clock for an AD9635 is from an FPGA PLL in LVDS. In this case, can I directly connect the PLL clock outputs to the clock inputs of AD9635 with capacitors and resistors without using a clock buffer such as AD951x in Fig 60 on page 22 of AD9635 data sheets? If yes, what is the input impedance, i.e. parallel resistors to ground and coupling capacitors?  Many thanks.

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	

		
	















	

	

					



			


				
	









	
    
	

  • 
	
    



	
			
		
	



    
	
    
		
    
							
					
    
		
    
			
													0
							
			
				
									
							        
            
                                                                                                        
      
                            
    • 
                                 Analog Employees 
                                
                            
      • 
                        
     
                                                           			
			                            
                        
                on Jan 23, 2018 2:28 AM
            
            
					
    
	
    

		
		
    
					
    Hi BCao,
    
 
    Thanks for your interest in AD9635. If your clock source is a driver that conforms to the LVDS standard, you do not need an additional buffer. The input impedance information of the clock pins is in Table 3 of the datasheet, but the main thing is to make sure that you have the 100Ohm LVDS termination on your board and are AC coupling to the clock pins.
    
 
    Please keep in mind that the clock generated from an FPGA will likely be noisy, so performance that you achieve with this clock will likely be lower than what is in the AD9635 datasheet.
    
 
    Thank you.
    
 
    Doug
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

    •