AD9694 - JESD204B setup

Hi,

Yes you are correct. L is set to two in each link. Two converters are mapped to each of the links. Four converters (two links) in total.

Judy

It looks like that means I can either use 1 Xilinx JESD204B receiver set to 4 lanes, or two separate receivers.

So Example 1 (Page 58 of the datasheet, "Full bandwidth mode") is really only discussing ONE link, not both?

Hi,

The Full Bandwidth Mode example in the datasheet demonstrates how to set up one of the links. If all four converters are to operate in full bandwidth mode at 500MSPS, both the links need to be set up the same way. The AD9694 doesn't support one link with L=4. The maximum throughput configuration requires two links at L=2 per link.

Judy

hi Judy, 

I have a related question: Is the above the reason ADI reference design (ZC706) connects one link (two JESD204 lanes) to one FPGA MGT (serdes) bank and the other one to another MGT bank? Can the two JESD204 links from AD9694 be connected to one MGT bank?

Thanks in advance.