I'm trying to understand the AD9694 - according to the datasheet, "By default, the AD9694 is configured to use four converters and four lanes."
However, it looks like that is *total* number of lanes, and that the device actually uses 2 lanes per *link*, and 2 converters per *lane*.Is this correct, or am I way off?
Yes you are correct. L is set to two in each link. Two converters are mapped to each of the links. Four converters (two links) in total.
It looks like that means I can either use 1 Xilinx JESD204B receiver set to 4 lanes, or two separate receivers.
So Example 1 (Page 58 of the datasheet, "Full bandwidth mode") is really only discussing ONE link, not both?
The Full Bandwidth Mode example in the datasheet demonstrates how to set up one of the links. If all four converters are to operate in full bandwidth mode at 500MSPS, both the links need to be set up the same way. The AD9694 doesn't support one link with L=4. The maximum throughput configuration requires two links at L=2 per link.