Products Mentioned

AD9689 Recommended for New Designs
The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed...
Datasheet
AD9689 on Analog.com

Associated Drivers

AD9698 Obsolete
The AD9696 and AD9698 are ultrafast TTL-compatible voltage comparators able to achieve propagation delays previously possible only in high performance...
Datasheet
AD9698 on Analog.com

Associated Drivers

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Regarding AD9689 modes of operation



		

			

									
					    Hajra
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 12, 2018 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    AD9689 has fS × 4 mode and full bandwidth mode as per datasheet. We would like to configure it in custome mode, where user can change JESD configuration parameters through SPI interface. Please let us know if this is possible with this ADC.
    
									
			        
		
    

				
						
        

    
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                 ad9689
                
                                                    
                 Analog Functions
                
                                                    
                 ad9698
                
                                                    
                 High Speed Comparators (<100ns Propagation Delay)
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                        
                                            
                
                
                                        
                                            
                
                
                                
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                on Feb 19, 2018 9:53 AM
            
            
					
        
	
        

		
		
        
					
        Hi Umesh,
        
 
          In Table 33 of AD9689 datasheet which shows list of JESD204B modes in full bandwidth mode has a configuration where M =2, L = 8, F = 2 , S = 4, HD = 0, N = 8 to 16, N` = 16, CS =0 to 3. In this configuration we have a quiry related to F and S values. If F = 2, in one clock do we get 4 samples of converter 1 in first 4 lanes and 4 samples of converter 2 in next 4 lanes?
        
 
        Thanks & Regards,
        
 
        Hajra
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Feb 19, 2018 9:53 AM
            
            
					
          
	
          

		
		
          
					
          Hi Umesh,
          
 
            In Table 33 of AD9689 datasheet which shows list of JESD204B modes in full bandwidth mode has a configuration where M =2, L = 8, F = 2 , S = 4, HD = 0, N = 8 to 16, N` = 16, CS =0 to 3. In this configuration we have a quiry related to F and S values. If F = 2, in one clock do we get 4 samples of converter 1 in first 4 lanes and 4 samples of converter 2 in next 4 lanes?
          
 
          Thanks & Regards,
          
 
          Hajra
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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