Why AD9864 output is noise when input IF signal is -90dBm

Hello,

I attached FFT plots that measure the fundamental as well as Integrated Noise Power in 10 KHz BW (includes spurs also).   FFT for -90 dBm shows that noise floor is still about 14 dB higher than one would expect if AD9864 was simply terminated at IF input with 270 ohm.   Hence, additional noise could be due to the noise contribution of IF driver stage to AD9864 IF input.   Increasing the signal level to -37 dbm shows a 12 dB increase in the Integrated Noise Power which could be due to the LO and CLK phase noise as well as the RF signal generator used to create the IF.  Typically one should use low noise RF generator as well as attenuators to reduce both signal and noise from generator.  For example, you could try adding 40 dB of attenuation at output generator and set  RF generator 40 dB higher to see if its noise contribution decreases.

1)  The -37 dBm input IQ data indicates that the Fundamental is at -15.3 dBFS.   If the IF input is properly impedance matched to compensate for match between 50 ohm RF generator and 270 IF input than I would expect a -44.3 dBm IF input level to result in -15.3 dBFS fundamental on FFT  (i.e. = -29 dBm-15.3 for VGA=0dB attenuation) .

***In your set-up with loss between RF generator..................a -21.7 dBm IF input results in 0 dBFS on ADC FFT.

2) As previously mentioned, I would not use the DVGA...........hence VGA attenuator can provide 12 dB attenuation.  Since the SSI data field is 8-bits, a 0x00 reading would correspond to 0 dB attenuation while a 0x3F reading would correspond to 12 dB attenuation (refer to figure 60 in datasheet).  A 6 dB attenuation setting would correspond to 0x20.

The SSI is a 6-bit word that goes from 0 to 63.    A value of 63 would correspond to "peak value" which is never reached since you need to operate with more than -2 dBFS back-off from full-scale.  Refer to last slide in attached PPT which shows how the SSI varies for a CW input at -2.5 dBFS (with AGC disabled).   If AGC were enabled...............the SSI work remains constant during the span where the ATTEN level is increased from 0 to 12 dB to ensure that the IF input level to the ADC stays below the AGC threshold setting (i.e. -3 dBFS).

3) Looking at your lines 26-31 for  Catch.jpg for Reg 0x06=0x02  (DVGA disabled with -6 dBFS AGC threshold)..................... the AGC starts reducing the ATTEN somewhere between -40 and -30 dBm  (lines 30 and 31).    At -30 dBm, one can see that the  ATTEN reads 0x0 (corresponding to 2.5 dB attenuation.....13/63*12dB) while SSI reads 0x18  (or -8.4 dBFS=20*log10(24/6.

If you continued to increase power from -30 dBm to -20 dBm..........you would expect to see ATTEN increase while SSI remain relatively stable until one reaches 12 dB of ATTEN.

4) The difference is that you have the DVGA enabled for line 60 and disabled for line 50.   The DVGA adds 12 dB of digital gain prior to 16-bit IQ quantization to reduce quantization noise but as I said before ...........it  has minimal improvement hence not using.   Since the AGC threshold is relative to the DVGA output (figure 59) for low level signals where DVGA is enabled for 1st 12 dB of range (and analog VGA for last 12 dB range) than one would expect to see the SSI data higher (for same IF dBm signal level ) hence explain the difference insSSI power.

 I would advice you to use the AD9864 EVB platform and software if you would like to get more familiar with the part and see how the AGC behaves real time by changing different parameters.   AGC behavior is difficult to explain thus best  evaluated directly with an EVB.