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Why AD9864 output is noise when input IF signal is -90dBm

Our product is using AD9864, by out test, when the input IF signal with level of -90dBm directly into AD9864, and the DSP capture AD9864 SSI output IQ data then draw it with Matlab, the data is almost noise, we can't see valid signal. For -70dBm input or -30dBm input, the IQ data looks ok.

So, what's the possible reason for my problem, hardware or AD9864 configuration issue? Could anyone help me? Also I want to know what's the smallest input level that AD9864 can accept.

Here is my AD9864 register setting. And my IF input freq is 73.35MHz, LO freq is 71.1MHz.


A few comments:

1) Table 24 shows an example SPI sequence for your exact same conditions (excluding the decimation factor and SSI port setting).  Are you following the same step-by-step procedure?

2) With regard to the SSI port settings, it seems like you are operating with 24-bit data and AGC data resulting in 64-bit frame.   With a decimation factor of 960 for CLK=18 MSPS, the Frame rate is 18.75 KSPS.  The minimum clock rate for SSI port must be greater than 1.2 MHz (=64 x 18.75 KSPS).   Your CLKOUT frequency is set to be also 1.2 MHz.

Wondering if increasing CLKOUT to 1.5 MHz  (SSIORD=0xC) provides some extra margin for AD9864 to push out data within one frame.

3)  If this does not work..............try using settings shown in Table 24 of datasheet for decimation factor and SSI port.
If this does not work............can you provide us with a file consisting of the captured IQ data.

4) The AD9864 has a very low NF (<9 dB) for narrowband signals below 10 KHz.   The integrated noise in 10 KHz would be -125 dBm hence device should be easily able to recover -90 dB input signal that has BW<10 KHz.


  • Hi, Thanks very much for your response. Here is my answer for your each comments.

    1) I can't find Table 24 in my AD9864 datasheet,  the last table in my datasheet is table 19. Is there another version of 9864 datasheet? If yes could you send me one? Here is my datasheet version

    2) My configuration is using 16 bit IQ data, and frame length is 48 bit. My SSICRB is 87 which means DW is 0(16 bit data).

    Also my decimation factor is 900, with CLK=18MHz, so frame rate is 20KHz. I think this part should be ok, am I right?

    3) I can't find table 24 to try it's setting but I can send you my IQ data captured also with the matlab graphic. It's good that you can help to analyze the data. I'll send you two groups of data, one is -30dBm 73.35MHz IF input, another one is -90dBm 73.35MHz IF input, both is modulated with 1KHz tone.

    This is graphic for -30dBm:

    zoom in for above one, can see it's 1k tone

    Then this is the bad one of -90dBm input:

    after zoom in it's almost noise.

    I don't know how to add attachment here, so I'll copy one line data here and send the whole raw ssi data files to you by email. One line data includes 1.25ms IQ data, totally number is 1.25ms*20KHz = 25 pairs IQ data.

    Below is raw ssi data for -90dBm. I want to say more about how to check the log. For example, the red one is 16 bit I data, but it's extended to 32 bit by log reason, so only the first 16 bit 000f is valid data. And the followed green one is 16 bit Q data, also be extended to 32 bit by log reason, so only the first 16 bit fffa is valid data.

    000f 0000 fffa ffff 0022 0000 ffda ffff 001f 0000 fffe ffff 0033 0000 ffec ffff 002d 0000 ffee ffff 0018 0000 0023 0000 fff8 ffff 0039 0000 0009 0000 0018 0000 fffd ffff ffeb ffff ffec ffff 0004 0000 ffda ffff fffc ffff fff1 ffff ffc4 ffff fffe ffff ffeb ffff 0016 0000 fffb ffff 0013 0000 ffe4 ffff ffea ffff ffef ffff ffe3 ffff fff7 ffff fff2 ffff ffeb ffff ffdb ffff ffee ffff ffee ffff ffe6 ffff 0002 0000 fffe ffff fff9 ffff 000d 0000 fffc ffff 0018 0000 ffd2 ffff 000e 0000 ffce ffff 001f 0000

    Below is raw ssi data for -30dBm.

    eb2e ffff 06e6 0000 ea51 ffff fcb8 ffff edca ffff f3dc ffff f3ba ffff edf2 ffff f9e0 ffff eb19 ffff fe91 ffff ea54 ffff 0122 0000 ea64 ffff 019c 0000 ea7d ffff 006a 0000 ea7e ffff fdf9 ffff ea9e ffff fae2 ffff eb20 ffff f7e4 ffff ec1a ffff f59c ffff ed33 ffff f47f ffff edda ffff f4b6 ffff eda9 ffff f6a5 ffff ec86 ffff fad6 ffff eaf0 ffff 0150 0000 ea41 ffff 093b 0000 ec2a ffff 10be 0000 f1db ffff 1557 0000 fae7 ffff 1558 0000 0516 0000 111f 0000 0dac 0000 0aa3 0000 1316 0000 043b 0000 1560 0000

    At last, is there any Hardware design that may cause this problem?

    Thanks again for your help!

  • Hello,

    1) Updated datasheet is on website................

    2) Based on you decimation factor of 900 and SSI frame length of should be fine with a clock rate of 1.5 MHz to capture all 48-bits within a frame.

    3) The IQ data looks odd for the -30 dBm (and -90 dBm case) since the I and Q waveforms have entirely different envelope characteristics (see plots below).  I would advise using simple CW tone that is 1 KHz offset (i.e no modulation) to simply debug.   Make sure that the AGC is disabled (0x06=0x0) set CW tone to around -37 dbm level into the AD9864 IF input (i.e. about -8 dBFS for a nominal IF clip point of -31 dBm) such that ADC is several dB below its saturation point.   Expectation is that one should see 1 KHz CW tone on both the I and Q output that are 90 degrees out of phase.

  • Hi PMH,

    Thanks your for your suggestion. I try your method that inject 73.351MHz(not 73.35MHz) as IF input signal, and capture the data. The result of -37dBm looks good, but the ssi raw data is very small when input level is -90dBm

    This is -37dBm IQ data

    This is -90dBm IQ data, you can see the amplitude is very small.

    Raw data is attached. In the txt file, the line with length 0064 is IQ data, the line with lenght 0032 is the last 16 bit of SSI data, which is ATTN+RSSI.

    I have another question about the ATTN and RSSI value in the last 16 bit SSI data, I am a little confused for these values.

    1). Set register 06 to 00 which disables AGC, when input IF is -70dBm, the IQ data is very very samll almost 0, and the last 16 bit data is about 0x2900(ATTN = 0x29,RSSI=0)

    2). Set register 06 to 81 which enables AGC, when input IF is -70dBm, the IQ data is bigger, and the last 16 bit data is 0x0000.

    So my question is:

    - What exactly ATTN and RSSI mean? What the relationship of them to AGC? The ATTN is introduced by AGC or by other component? In my mind, when the signal is small, the AGC should amplifies the small signal, right?
  • Hello,

    It now appears that you are capturing data correctly.  

    Referring to figure 67 of the AD9864 Rev A datasheet,  the BW=10 KHz curve suggests that you should achieve an SNR-dBFS of around 94.1 dBFS when the VGA attenuation is set to 0 dB.  Note that this assumes no contribution from any prior driver stage in front of the AD9864.   The "IF clip point" (being -2 dBFS) is specified as nominal -31 dBm hence -29 dBm corresponds to 0 dBFS full-scale.   Hence, for a -37 dBm signal, I would expect a high SNR-dBc around 86.1 dBc (=94.1 dBFS - 8 dBFS) assuming phase noise is not an issue.   Reducing the signal to -90 dBm corresponds to a reduction of 53 dB hence one would expect the SNR-dBc to be around 33.1 dBc.

    Unfortunately I do not have script to extract I and Q data so difficult to generate FFT plot with measured SNR with Visual Analog software tool we use.  Feel free to resend data in I + j Q format and I could measure SNR and observe FFT spectrum.

    Answer to other questions are as follows:

    1) Not sure why ATTEN=0x29 when input signal is -70 dBm with or without AGC since this falls well below the AGC threshold set by the AGCR field in 0x06.  Note that an  If you disable AGC by setting 0x06 to should also set AGCG setting in 0x04 and 0x03 to "0" so no attenuation is applied to input signals (when testing with signals below IF clip point of -31 dBm).   I would expect that the ATTEN field in the SSI data stream would reflect the settings in the AGCG field (0x06) when AGC is disabled.  Note.............the RSSI field  looks correct since it has insufficient resolution (being 6-bits) to detect signals that low.  I would expect the RSSI field to start changing "0" value around -65 dBm signal level (with ATTEN=0x00).

    2) My advice is to not to use the DVGA function since it really has minimal benefit. Only under large signal conditions when AGC causes ATTEN to increase from 0 to 12 dB will one see a slight improvement in SNR...........BUT one could argue that one will have more than sufficient SNR performance to demodulate a "large desired signal" or in case if it is narrowband blocker at 25 KHz offset.................the phase noise of blocker will dominate over thermal noise hence no real benefit.  Lastly, thermal of the RF-to-IF front end will likely be several dB higher than the AD9864's NF.   Perhaps best to operate with 0x06=0x01 instead of 0x81.


  • Hi PMH,

    I attach the I and Q data for you.

    Also i measured the SSI last 16 bits(ATTN+RSSI) for different reg setting and different input IF signal level. The result is as below table. But I still have some question as below. One note that my signal generater may have some RF loss that input -30dBm the actual value is -34dBm, so I set reg06 to 82 not 81.

    1) Only for the condition of reg06 = 82/81, the RSSI field is to start changing "0" value around -65 dBm signal level (with ATTEN=0x00). For other case, the RSSI filed starts changing 0 after input level is bigger than -60dBm.

    2) How to calculate the estimated RSSI with the SSI last 16 bits? For example, in table line 15, the estimated RSSI = -(65dBm - 11dBm) = -54dBm? What about line 16 with ATTN is not zero?

    3) What does ATTN exactly mean here? For example from table line 15 to 16, the ATTN is changing from 00 to 26, what can I do with this value?

    4) Compare to line 45 and line 50, the difference is ATTN is changed from 0 to 1, could you explain why it changes like this?

    Sorry that I have so many questions to bother you.
  • Hello,

    I attached FFT plots that measure the fundamental as well as Integrated Noise Power in 10 KHz BW (includes spurs also).   FFT for -90 dBm shows that noise floor is still about 14 dB higher than one would expect if AD9864 was simply terminated at IF input with 270 ohm.   Hence, additional noise could be due to the noise contribution of IF driver stage to AD9864 IF input.   Increasing the signal level to -37 dbm shows a 12 dB increase in the Integrated Noise Power which could be due to the LO and CLK phase noise as well as the RF signal generator used to create the IF.  Typically one should use low noise RF generator as well as attenuators to reduce both signal and noise from generator.  For example, you could try adding 40 dB of attenuation at output generator and set  RF generator 40 dB higher to see if its noise contribution decreases.

    1)  The -37 dBm input IQ data indicates that the Fundamental is at -15.3 dBFS.   If the IF input is properly impedance matched to compensate for match between 50 ohm RF generator and 270 IF input than I would expect a -44.3 dBm IF input level to result in -15.3 dBFS fundamental on FFT  (i.e. = -29 dBm-15.3 for VGA=0dB attenuation) .

    ***In your set-up with loss between RF generator..................a -21.7 dBm IF input results in 0 dBFS on ADC FFT.

    2) As previously mentioned, I would not use the DVGA...........hence VGA attenuator can provide 12 dB attenuation.  Since the SSI data field is 8-bits, a 0x00 reading would correspond to 0 dB attenuation while a 0x3F reading would correspond to 12 dB attenuation (refer to figure 60 in datasheet).  A 6 dB attenuation setting would correspond to 0x20.

    The SSI is a 6-bit word that goes from 0 to 63.    A value of 63 would correspond to "peak value" which is never reached since you need to operate with more than -2 dBFS back-off from full-scale.  Refer to last slide in attached PPT which shows how the SSI varies for a CW input at -2.5 dBFS (with AGC disabled).   If AGC were enabled...............the SSI work remains constant during the span where the ATTEN level is increased from 0 to 12 dB to ensure that the IF input level to the ADC stays below the AGC threshold setting (i.e. -3 dBFS).

    3) Looking at your lines 26-31 for  Catch.jpg for Reg 0x06=0x02  (DVGA disabled with -6 dBFS AGC threshold)..................... the AGC starts reducing the ATTEN somewhere between -40 and -30 dBm  (lines 30 and 31).    At -30 dBm, one can see that the  ATTEN reads 0x0 (corresponding to 2.5 dB attenuation.....13/63*12dB) while SSI reads 0x18  (or -8.4 dBFS=20*log10(24/6.

    If you continued to increase power from -30 dBm to -20 would expect to see ATTEN increase while SSI remain relatively stable until one reaches 12 dB of ATTEN.

    4) The difference is that you have the DVGA enabled for line 60 and disabled for line 50.   The DVGA adds 12 dB of digital gain prior to 16-bit IQ quantization to reduce quantization noise but as I said before  has minimal improvement hence not using.   Since the AGC threshold is relative to the DVGA output (figure 59) for low level signals where DVGA is enabled for 1st 12 dB of range (and analog VGA for last 12 dB range) than one would expect to see the SSI data higher (for same IF dBm signal level ) hence explain the difference insSSI power.

     I would advice you to use the AD9864 EVB platform and software if you would like to get more familiar with the part and see how the AGC behaves real time by changing different parameters.   AGC behavior is difficult to explain thus best  evaluated directly with an EVB.

  • Hi PMH,

    I don't have any other questions now. I am going to buy one EVB board to do test.

    You did great help to me, how should I thank you for this? I there any feedback system of your company that I want to thumb up for you.

  • Hello,

    Thanks for your kind words.  Not sure if any feedback system exists but I am just glad to be helpful.