We are using the AD9625-2.0 component in our design.
I wanted to ask about the clock mechanism, as its not clear from the datasheet.
We input at CLK± input 240MHz clock. This is the also the clock used for JESD2004B. As the samples are composed of 20bits, each lane has 4.8Gbps.
When inputting 240MHz, this clock would be used to create the sample clock of 1920MSPS to sample the RF analog signal.
We have two bands that we need to sample with 1920MSPS, and output them using the JESD2004B 4lanes (I0, Q0, I1, Q1)
The datasheet , at page 7, mentions clock rate of 330MSPS up to 2000MSPS. We don’t understand the meaning of that:
- Is this the clock in range MHz at the CLK± input. (and therefore I cannot input 240MHz)
- The clock input CLK± is 165MHz to 1000MHz (as 2MSPS is known to be 1MHz)
- This is the sample clock created inside the part from the CLK± input. (we need a multiple of 8 from 240MHz to 1920MSPS)
Which one of the options is correct and possible?
[edited by: Noamm75 at 7:48 AM (GMT 0) on 8 Jul 2020]