When the CML input and output ports of the hmc series devices are connected to the LVDS or LVPECL interface of the FPGA, how should the capacitance value be determined? For example, HMC749, the D output port of the T flip-flop, it only changes once, and then the level of this port is sent to the FPGA. If so, does AC coupling cut off this level signal.
In addition, I control the enable port of the HMC749 T flip-flop through the signal output from the FPGA. Can I also use AC coupling? And I should use DC coupling.
If AC coupling is used, how should I determine the value of the capacitor