How should the CML level standard IO pin of HMC746 be connected with FPGA
How should the CML level standard IO pin of HMC746 be connected with FPGA
What is the interface standard you have on your FPGA? Is it LVDS, ECL or similar? What is the reference voltage, 1.8, 2.5, 3.3, 5 ? We can figure out the interface if you could tell us the interface standard, the swing, and the termination voltage.
Please also refer to the applicaiton note attached. There are several interface examples for CML & FPGA...
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