How should the CML level standard IO pin of HMC746 be connected with FPGA
HMC746
Recommended for New Designs
The HMC746LC3C is an AND/NAND/OR/NOR function designed to support data transmission rates of up to 14 Gbps, and clock frequencies as high as 14 GHz. The...
Datasheet
HMC746 on Analog.com
How should the CML level standard IO pin of HMC746 be connected with FPGA
What is the interface standard you have on your FPGA? Is it LVDS, ECL or similar? What is the reference voltage, 1.8, 2.5, 3.3, 5 ? We can figure out the interface if you could tell us the interface standard, the swing, and the termination voltage.
Please also refer to the applicaiton note attached. There are several interface examples for CML & FPGA...PDF
Thanks
But,I would like to ask, how to send the single-ended HMC746 into the FPGA, that is to say, only need to use its single-ended. Last time I didn’t make it clear, sorry
LVCMOS etc